Semiconductor Layout Patterning Groups for Routing Optimization

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Solution Overview

Problem

The challenge in semiconductor device manufacturing lies in creating high-reliability, high-performance devices with increased complexity and integration density while efficiently connecting power and input patterns, which existing methods struggle to achieve due to limitations in photolithography processes and routing complexity.

Innovation Solution

The method involves preparing a layout pattern for a semiconductor device that includes selecting power patterns, input patterns, and tie-connection patterns to form metal lines on a substrate using multiple photomasks, with back-annotation information guiding the selection of tie-connection patterns to optimize connections and reduce routing distances, thereby improving device performance and efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple photomasks are used to form metal lines according to distinct patterning groups, then the connection efficiency between power and input patterns is improved and routing distance is reduced, but the device complexity and manufacturing process complexity increase

Engineering Contradiction:
Improveconnection efficiencyVSAvoidpatterning group complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the metal line formation process into multiple patterning groups, where each photomask handles specific patterns (power patterns, input patterns, tie-connection patterns). This segmentation allows optimized routing for each pattern type while managing overall complexity through systematic organization of the fabrication process.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension of organization by creating distinct patterning groups that classify patterns based on their function and connection requirements. This dimensional classification enables more efficient routing decisions and reduces overall routing distance by systematically assigning patterns to appropriate photomasks.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Speed

If tie-connection patterns are used to connect power and input patterns, then the routing distance is reduced and device performance is improved, but the layout complexity and manufacturing precision requirements increase

Engineering Contradiction:
Improveoperation speedVSAvoidlayout precision
Core Design Contradiction:
SpeedVSManufacturing precision

Solution Approach 1:

The patent performs preliminary classification of patterns into distinct patterning groups before the actual photomask fabrication. By pre-organizing power patterns, input patterns, and tie-connection patterns into specific groups, the system enables more precise and efficient manufacturing with reduced routing distances and optimized operation speed.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces tie-connection patterns as intermediary elements that specifically connect power patterns to input patterns. These intermediary tie-connection patterns optimize the electrical connection path, reducing routing distance and improving operation speed while maintaining manageable manufacturing precision through systematic pattern classification.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If back-annotation information is used to guide tie-connection pattern selection, then the manufacturing efficiency is improved and routing optimization is achieved, but the information processing complexity and device complexity increase

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidinformation processing complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements back-annotation information that provides feedback about pattern compatibility and connection feasibility. This feedback mechanism guides the selection of tie-connection patterns by indicating which patterns can be effectively connected, thereby improving manufacturing efficiency and routing optimization while managing information processing complexity through structured data organization.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9846754B2Method of fabricating semiconductor device
Publication Date: 2017.12.19 SAMSUNG ELECTRONICS CO LTD
  • US9846754B2 patent drawing
  • US9846754B2 patent drawing
  • US9846754B2 patent drawing

AI summary

A semiconductor device can be manufactured based on patterning groups to include a metal layer patterned according to separate patterning groups. The patterning groups are based on a layout pattern. Preparing the layout pattern includes selecting a first power pattern and a second power pattern, selecting a first pattern and a second pattern therebetween, and selecting a tie-connection pattern to connect the first power pattern to the first pattern. The manufacturing includes forming metal lines according to the patterning groups. Photomasks are manufactured according to the layout pattern, and the metal lines are formed according to the photomasks. A first photomask is manufactured based on the first power pattern and the second power pattern, the first pattern, and the tie-connection pattern, and a second photomask is manufactured based on the second pattern.