Semiconductor Interconnect Layout With Post-Routing Pin Pattern Shrink

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Solution Overview

Problem

The increasing demand for high-performance, low-power consumption semiconductor devices with increased complexity and integration density poses challenges in designing and manufacturing semiconductor devices with efficient interconnections, as existing methods struggle to optimize pin patterns and vias for improved performance and reliability.

Innovation Solution

A method is introduced that involves creating a preliminary pin pattern, performing a routing step to generate a high-level interconnection layout, and producing a postliminary pin pattern based on hitting information, which allows for the optimization of pin patterns and vias to enhance semiconductor device performance and reduce parasitic capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a preliminary pin pattern is created and routing is performed to generate high-level interconnection layout, then the degree of freedom in routing is maximized, but the pin pattern size is reduced requiring post-routing optimization

Engineering Contradiction:

Improvedegree of freedom in routingVSAvoidpin pattern size

Core Design Contradiction:

Adaptability or versatilityVSArea of moving object

Solution Approach 1:

The patent applies preliminary action by first creating a preliminary pin pattern before routing, allowing the routing process to have maximum flexibility. After routing is completed and hitting information is obtained, the pin pattern is then optimized to its final smaller size. This two-stage approach enables routing freedom during the intermediate stage while achieving compact final dimensions.

Inventive Principle:

Principle #10Preliminary action

2Loss of energy

If pin pattern size is minimized to reduce parasitic capacitance, then power consumption is reduced, but routing flexibility is constrained

Engineering Contradiction:

Improvepower consumptionVSAvoidrouting flexibility

Core Design Contradiction:

Loss of energyVSAdaptability or versatility

Solution Approach 1:

The patent resolves this contradiction by performing the pin pattern size optimization as a preliminary action before routing. By establishing the pin pattern at its final optimized size beforehand, the routing process can work with fixed endpoints, ensuring minimal parasitic capacitance while still achieving valid routing connections through the hitting information mechanism.

Inventive Principle:

Principle #10Preliminary action

3Ease of manufacture

If standard cell layouts are designed with fixed pin patterns, then manufacturing is simplified, but performance optimization is limited

Engineering Contradiction:

Improvestandard cell layout fabricationVSAvoiddevice performance

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent segments the pin pattern design into two distinct phases: a preliminary pin pattern creation phase that maintains manufacturing simplicity through standardized initial patterns, and a post-routing optimization phase that adjusts the pin pattern based on hitting information to achieve performance optimization. This segmentation allows both ease of manufacture and performance improvement to coexist.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUSRE49780E1Methods of designing a layout of a semiconductor device including field effect transistor and methods of manufacturing a semiconductor device using the same

Publication Date: 2024.01.02 SAMSUNG ELECTRONICS CO LTD

AI summary

A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.