Semiconductor Layout Design Power Distribution Network Verification
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Solution Overview
Problem
Existing layout-versus-schematic (LVS) verification methods for semiconductor devices are complex and inefficient for verifying power distribution networks, particularly in ensuring minimum resistance in the power distribution network.
Innovation Solution
A method and system for designing a power distribution network in semiconductor devices that involves verifying the network by designing a layout with a power wiring pattern, extracting top and next-top layer wiring patterns connected to bumps, determining their interconnectivity, and modifying the layout accordingly to ensure minimum resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing LVS verification methods are used to verify power distribution networks, then connectivity of wirings for entire layers can be verified, but the verification process becomes complex and inefficient
Solution Approach 1:
The patent segments the power distribution network verification into distinct layers: extracting top layer wiring patterns connected to bumps, extracting next-top layer wiring patterns connected to bumps, and determining interconnectivity between these extracted patterns. This segmentation allows verification to focus on critical power distribution paths rather than analyzing all wirings across entire layers, thereby simplifying the verification process while maintaining reliability
Solution Approach 2:
The patent extracts only the relevant wiring patterns from the power distribution network - specifically, top layer wiring patterns connected to bumps and next-top layer wiring patterns connected to bumps. By extracting and isolating these critical components for verification, the method avoids the complexity of analyzing the entire power distribution network while ensuring key power delivery paths are validated
2Reliability
If existing LVS verification methods are used to verify power distribution networks, then connectivity of wirings for entire layers can be verified, but verification efficiency decreases
Solution Approach 1:
The verification process is segmented into focused steps: extract top layer patterns connected to bumps, extract next-top layer patterns connected to bumps, determine interconnectivity between these extracted patterns, and modify layout if needed. This segmentation improves verification efficiency by concentrating computational resources on the most critical power distribution paths rather than processing all wiring layers comprehensively
Solution Approach 2:
The patent extracts only the essential wiring patterns involved in power distribution - those connected to bumps on the top and next-top layers. This extraction significantly reduces the verification scope and computational burden while maintaining reliability by focusing on the key power delivery paths that most impact device performance
Data Source
AI summary
Provided is a method of designing a layout of a semiconductor device including a plurality of wiring layers, the method including verifying a power distribution network, the verifying of the power distribution network including designing a layout including a power wiring pattern, extracting a top layer wiring pattern and a next-top layer wiring pattern connected to bumps in the power wiring pattern, determining whether the top layer wiring pattern and the next-top layer wiring pattern are interconnected, and modifying the layout based on whether the top layer wiring pattern and the next-top layer wiring pattern are interconnected.