Semiconductor Layout Simulation for Process-Margin Stability
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Solution Overview
Problem
Existing semiconductor layout design methods face challenges when process margins are considered after layout design is completed, leading to changes in the already designed layout.
Innovation Solution
A layout design method that generates a first layout, performs simulation, considers process margins, and adjusts layouts to satisfy target values through optical proximity correction, ensuring accurate and consistent design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If process margin is considered after layout design is completed, then manufacturing precision is improved, but layout stability deteriorates due to changes in already designed layout
Solution Approach 1:
The patent applies preliminary action by performing simulation and calculating process margins during the layout design phase itself, rather than after completion. The design system generates multiple candidate layouts, simulates their manufacturing outcomes, and selects optimized layouts that already account for process variations. This prevents the need for post-design modifications and maintains layout stability while achieving manufacturing precision.
2Manufacturing precision
If layout is modified to consider process margin, then manufacturing precision is improved, but design complexity increases due to additional simulation and calculation steps
Solution Approach 1:
The design system performs self-service by automatically conducting simulations, calculating process margins, and optimizing layouts without requiring manual intervention. The system integrates simulation and margin calculation directly into the automated layout design workflow, allowing the design tool to self-correct and self-optimize layouts based on manufacturing considerations, thereby managing complexity through automation rather than manual processes.
3Manufacturing precision
If simulation is performed on first layout to generate second layout, then manufacturing precision is improved, but design time increases due to additional simulation steps
Solution Approach 1:
The patent applies partial action by performing simulation selectively on critical layout elements or representative samples rather than exhaustively simulating every possible design iteration. The system calculates process margins for key parameters and uses this information to guide layout optimization, performing sufficient simulation to achieve manufacturing precision without unnecessary exhaustive analysis, thereby balancing accuracy with design time efficiency.
Data Source
AI summary
Provided is a layout design method including generating a first layout of an integrated circuit, performing first simulation on the first layout, generating a second layout considering the first simulation and a process margin, extracting a first calculated value based on the first layout and a second calculated value based on the second layout, and generating a final layout that satisfies a target value based on the first calculated value and the second calculated value, wherein the first calculated value and the second calculated value may be values calculated by circuit structures corresponding to the first layout and the second layout, respectively.