Semiconductor Layout Redundant Via Generation for Defect Mitigation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor device fabrication lies in achieving improved yield, reliability, and processability, particularly in miniaturized devices, where existing methods struggle to effectively predict and address potential defects in the design layout.
Innovation Solution
A method involving a database-driven prediction model using machine learning to identify target patterns in semiconductor device layouts, generating redundant nets and vias based on peripheral patterns, and checking these against predetermined design rules to enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If machine learning prediction model is used to identify bad patterns, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by using machine learning prediction models to identify potentially defective patterns before actual fabrication occurs. The system analyzes design layouts in advance, predicts bad patterns based on historical data, and flaggs them for review, thereby preventing defects from reaching production while maintaining manageable process complexity through automated prediction.
Solution Approach 2:
The patent implements feedback mechanisms where the machine learning model continuously learns from historical fabrication data and outcome information. The system feeds back results of pattern analysis and defect detection to refine future predictions, improving reliability over time while the automated feedback loop manages complexity by handling iterative improvements automatically.
2Reliability
If redundant nets and vias are generated to mitigate defects, then reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies beforehand cushioning by generating redundant nets and vias as preventive measures against potential fabrication defects. These redundant elements act as cushions or safety margins that can compensate for process variations and defects, improving yield without requiring extremely tight manufacturing precision specifications.
Solution Approach 2:
The system dynamically adjusts design parameters by modifying the generation of redundant nets and vias based on analyzed peripheral patterns and predicted defect locations. By changing these layout parameters strategically, the system improves reliability while maintaining compliance with standard design rules through automated parameter optimization.
3Manufacturing precision
If analysis of peripheral patterns is performed, then manufacturing precision is improved, but loss of time increases
Solution Approach 1:
The patent performs preliminary analysis of peripheral patterns around suspected bad patterns before finalizing the design. This advance analysis identifies areas requiring redundant elements, allowing the system to prepare mitigation strategies in advance and reduce overall fabrication cycle time by avoiding late-stage redesigns.
Solution Approach 2:
The system creates virtual copies or representations of the design layout for analysis purposes. By working with digital models and simulations of the peripheral patterns, the system can perform precise analysis without physically modifying or delaying the actual fabrication process, thereby maintaining manufacturing precision while minimizing time loss.
Data Source
AI summary
Methods of fabricating semiconductor devices are provided. A method of fabricating a semiconductor device includes selecting a target pattern from a target design layout. The target pattern includes: a target net; a target via that is electrically connected to the target net; and a crossing net that is electrically connected to the target via on a different level from the target net. The method includes analyzing a peripheral pattern that is adjacent the target net. Moreover, the method includes generating a redundant net, and a redundant via that electrically connects the redundant net and the crossing net. Related layout design systems are also provided.