Semiconductor Layout Rule Updates for Plasma Damage Prevention
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Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in preventing or reducing failures such as gate dielectric layer breaks, channel region burns, and gate electrode burns, which are exacerbated by the downsizing of components and reduced distances between components.
Innovation Solution
A manufacturing method that involves determining and updating design rules based on failure evaluations, redesigning semiconductor device layouts, and performing simulations to ensure compliance with updated design rules, thereby minimizing failures by adjusting spacing and area regulations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If component sizes are reduced and distances between components are decreased to achieve down-scaling, then device integration density is improved, but reliability deteriorates due to increased susceptibility to plasma-induced damage and antenna effects
Solution Approach 1:
The patent applies preliminary action by performing failure evaluation simulations before actual device manufacturing. The design rule determination process uses simulated plasma processing and antenna effect calculations to identify potential failure locations in advance, allowing design rules to be updated proactively to prevent failures before they occur in production devices.
Solution Approach 2:
The patent implements feedback through an iterative process where failure evaluations are performed on simulated devices, design rules are determined or updated based on results, and the process repeats. This closed-loop feedback mechanism continuously refines design rules to improve reliability while maintaining down-scaling benefits, as evidenced by the repeated cycles of simulation, evaluation, and rule updating described in the embodiments.
2Reliability
If design rules are updated based on failure evaluations to prevent gate dielectric layer breaks and channel region burns, then reliability is improved, but manufacturing complexity increases due to additional simulation and rule determination steps
Solution Approach 1:
The patent uses copying by creating simulated semiconductor devices that replicate the structural and electrical characteristics of actual devices. These virtual copies undergo failure evaluation simulations, allowing design rules to be determined without physically manufacturing and testing each device iteration. The simulation models copy plasma processing effects and antenna calculations to predict failures, reducing the need for physical trial-and-error manufacturing.
3Reliability
If spacing and area regulations are adjusted to minimize antenna effects and plasma-induced damage, then failure occurrence is reduced, but design flexibility is constrained
Solution Approach 1:
The patent applies local quality by implementing spatially varying design rules based on local failure risks. Different spacing and area regulations are applied to different regions of the semiconductor device depending on their susceptibility to plasma-induced damage and antenna effects. The system calculates antenna ratios and plasma charging effects locally for each conductor configuration, allowing optimized rules specific to each device region rather than applying uniform constraints throughout.
Data Source
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AI summary
A method of manufacturing a semiconductor device includes designing a semiconductor device layout using a design rule manual, DRM, in which design rules are recorded (S110), and performing failure evaluation of a failure (S160). The method further includes updating the DRM by updating the design rules recorded in the DRM, based on a result of the failure evaluation (S170), redesigning the semiconductor device layout using the updated DRM (S110a), and manufacturing the semiconductor device using the redesigned semiconductor device layout (S300).