Semiconductor Layout Design with Shared Border Terminations

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Solution Overview

Problem

Current layout design systems for semiconductor devices face challenges in miniaturization and integration, as they often require additional termination components that occupy space and hinder the compact design of semiconductor devices.

Innovation Solution

A layout design system that generates a second unit design with a larger area by placing terminations such as dummy gate electrodes and active fins on the borders of first unit designs, allowing for the reduction of space occupied by these components and enabling miniaturization of semiconductor devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If termination components are placed on the borders of unit designs, then the reliability and functionality of the semiconductor device are improved, but the area occupied by these components increases, hindering miniaturization

Engineering Contradiction:
Improvedevice reliabilityVSAvoidborder area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the termination components with adjacent unit designs by sharing border areas. When multiple unit designs are placed adjacent to each other, the termination at their common border serves both unit designs simultaneously, eliminating the need for separate termination areas for each unit and thereby reducing the total border area occupied.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The termination components at shared borders serve multiple functions: they provide proper termination for multiple adjacent unit designs simultaneously and can also serve as buffer regions for signal integrity. This multi-functionality allows the same area to fulfill multiple purposes, reducing overall device area while maintaining reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If termination components are placed on the borders of unit designs, then the functionality of individual units is ensured, but the device complexity increases due to additional components

Engineering Contradiction:
Improveunit design functionalityVSAvoidstructure complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

By merging termination components across adjacent unit designs, the patent reduces the total number of termination components needed. Instead of having separate terminations for each unit design border, shared terminations serve multiple units, thereby reducing structural complexity while maintaining the functionality of each individual unit.

Inventive Principle:
Principle #5Merging (Combining)

3Area of stationary object

If termination-free unit designs are used, then the area is reduced enabling miniaturization, but the reliability may be compromised without proper termination

Engineering Contradiction:
Improvedevice areaVSAvoiddevice reliability
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent combines unit designs in such a way that termination requirements are satisfied at the aggregate level rather than at each individual unit level. By strategically placing and sharing termination components at boundaries between unit designs, the system achieves proper termination while maintaining termination-free interiors, thus reducing area while preserving reliability.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9633161B2Layout design system, method, and semiconductor device employing termination-free unit designs
Publication Date: 2017.04.25 SAMSUNG ELECTRONICS CO LTD
  • US9633161B2 patent drawing
  • US9633161B2 patent drawing
  • US9633161B2 patent drawing

AI summary

A layout design system includes a processor; a storage unit configured to store a first unit design having a first area, wherein in the first unit design, a termination is not placed on a border thereof; and a design module configured to generate a second unit design having a second area larger than the first area by placing the termination on a border of the first unit.