Semiconductor Module Layout for Low-Inductance Short-Circuit Stability
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing oscillation between blocks during short circuits due to high internal inductance, which is not adequately addressed by existing techniques that only reduce inductance between upper and lower arms.
Innovation Solution
The semiconductor device employs a configuration with insulating substrates, semiconductor elements connected in series, and metal patterns that are electrically connected in specific arrangements to reduce inductance and oscillation, using conductive portions to connect metal patterns without direct electrical connections between semiconductor elements, and optimizing the layout to maintain device size and balance inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of semiconductor elements is increased to improve power capacity, then power handling capability is improved, but internal inductance increases and oscillation increases
Solution Approach 1:
The patent segments the semiconductor device into multiple independent blocks (first block with first and second semiconductor elements, second block with third and fourth semiconductor elements), each with its own metal patterns and terminals. This segmentation allows each block to be optimized independently while reducing mutual interference and inductance between elements, enabling power capacity increase without proportional increase in oscillation.
Solution Approach 2:
The patent merges the AC terminal connections of different blocks through the conductive portion connecting the second metal pattern and the fifth metal pattern. This merging creates a common reference potential that reduces the overall inductance of the system, allowing multiple semiconductor elements to be used for increased power capacity without the inductance and oscillation problems that would normally accompany element multiplication.
2Reliability
If metal patterns are arranged to reduce inductance between upper and lower arms, then inductance within block is reduced, but device complexity increases
Solution Approach 1:
The patent employs asymmetric arrangement of metal patterns within each block, where the first metal pattern is electrically connected to the first semiconductor element without being connected to the second semiconductor element, while the second metal pattern is electrically connected to both semiconductor elements. This asymmetric configuration optimizes current paths to reduce inductance while maintaining manufacturing feasibility and avoiding excessive complexity.
Data Source
AI summary
A semiconductor device includes: a second metal pattern electrically connected to a first semiconductor element and a second semiconductor element; a third metal pattern electrically connected to the second semiconductor element; a fifth metal pattern electrically connected to the third semiconductor element and a fourth semiconductor element; a sixth metal pattern electrically connected to the fourth semiconductor element; and a first conductive portion straddling the third metal pattern and the sixth metal pattern in plan view and electrically connecting the second metal pattern and the fifth metal pattern.