Semiconductor IC Layout with Slot and Island Conductors
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Solution Overview
Problem
Conventional semiconductor IC fabrication processes face challenges in achieving high resolution and overlay accuracy, especially when feature sizes decrease below 85 nanometers, leading to increased process complexity and cost with multiple patterning technologies, and there is a need to improve process yield and reduce complexity in IC layout structures.
Innovation Solution
The semiconductor IC layout structures incorporate slot-type and island-type conductive structures formed in a single layer, which simplify the layout design without affecting electrical connections, and the use of multiple wire structures extending in different directions in the same layer for INV, ND2, and XOR2 layouts, allowing for improved fabrication and reduced complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple patterning technology is used to achieve smaller feature sizes below 85nm, then manufacturing precision is improved, but device complexity and process cost increase
Solution Approach 1:
The patent applies segmentation by dividing the dense layout pattern into sub-patterns that can be printed using available lithographic equipment. The layout is decomposed such that each sub-pattern can be formed with existing single-patterning capabilities, avoiding the need for complex multiple patterning processes while still achieving the required small feature sizes below 85nm.
Solution Approach 2:
The patent utilizes dimensional optimization by arranging conductive structures in specific geometric configurations (such as merged conductive structures spanning across active regions) that allow dense packing without requiring multiple patterning steps. The layout optimizes the use of planar space to achieve high density while maintaining manufacturability with single-patterning processes.
2Manufacturing precision
If multiple patterning technology is used to create densely packed devices, then manufacturing precision is improved, but process cost increases
Solution Approach 1:
The layout is segmented into sub-patterns that align with the capabilities of existing lithographic equipment. By decomposing the dense pattern into manageable sub-patterns, the patent achieves high resolution without incurring the additional costs of multiple patterning processes, thereby reducing process cost while maintaining pattern resolution.
Solution Approach 2:
The patent optimizes layout parameters such as conductor width, spacing, and arrangement to achieve dense packing within the constraints of single-patterning lithography. By carefully adjusting these geometric parameters, the design achieves the required pattern resolution using existing equipment, avoiding the need for expensive multiple patterning processes.
3Quantity of substance
If conventional layout structures are used with decreasing feature sizes, then device density increases, but process yield decreases due to stringent resolution and overlay accuracy requirements
Solution Approach 1:
The patent segments the layout into sub-patterns that are less sensitive to overlay errors and resolution limitations. By dividing the dense pattern into smaller, more manageable features, the design maintains high device density while reducing the impact of process variations, thereby improving process yield.
Solution Approach 2:
The patent incorporates preliminary design optimizations in the layout stage that pre-compensate for potential process variations. The conductive structure configurations are designed to be inherently robust against overlay errors and resolution limitations, ensuring high process yield before fabrication begins.
Data Source
AI summary
A semiconductor IC layout structure includes a plurality of first active regions arranged along a second direction, a plurality of second active regions arranged along the second direction, a plurality of gate structures extending along a first direction and respectively straddling the first active regions and the second active regions, a plurality of first conductive structures extending along the first direction, and a plurality of second conductive structures formed on the gate structures. The second active regions are isolated from the first active regions. The first direction is perpendicular to the second direction. The first conductive structures are formed on the first active regions and the second active regions. The second conductive structures include a plurality of slot-type second conductive structures extended along the second direction and a plurality of island-type second conductive structures formed on the gate structures.