Semiconductor Layout Splitting for Double Patterning Overlay Control
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Solution Overview
Problem
The conventional double patterning technique (DPT) in semiconductor fabrication faces challenges with overlay control and alignment issues, leading to line-end shortening and split pattern breaks, which increase manufacturing complexity and cost.
Innovation Solution
The method involves defining to-be-split patterns in semiconductor layouts and corresponding connection patterns, decomposing the layouts into multiple masks, and using a double patterning technique to ensure that connection patterns are formed even in cases of overlay errors or line-end shortening, thereby preventing line breaks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If double patterning technique is used to increase half-pitch resolution, then manufacturing precision is improved, but device complexity increases due to overlay control and alignment requirements
Solution Approach 1:
The patent segments the original layout pattern into two separate masks (first mask and second mask), each containing specific layout patterns. This segmentation allows the double patterning technique to increase half-pitch resolution by forming patterns that would be too fine to print with a single exposure, while managing complexity through systematic decomposition of the patterning process into distinct stages.
Solution Approach 2:
The patent applies preliminary action by performing alignment mark formation and overlay calibration before the actual pattern transfer. Alignment marks are formed on both masks in advance, and the system performs overlay control measurements and adjustments prior to production patterning. This preliminary preparation reduces complexity during manufacturing by establishing precise registration early in the process.
2Manufacturing precision
If to-be-split patterns are used to decompose original layout, then manufacturing precision is improved, but reliability deteriorates due to line-end shortening and split pattern breaks
Solution Approach 1:
The patent introduces alignment marks as intermediary elements that mediate between the two masks during the double patterning process. These alignment marks do not participate in the final circuit pattern but serve as reference features that enable precise overlay control. By providing this intermediary reference system, the patent ensures that split patterns from the first and second masks align correctly, preventing line breaks and maintaining reliability despite the complexity of pattern decomposition.
3Manufacturing precision
If conventional DPT is used for pattern decomposition, then manufacturing precision is improved, but ease of manufacture deteriorates due to overlay control and line-end shortening issues
Solution Approach 1:
The patent implements self-service through self-aligned mandrel formation and self-correcting alignment mark systems. The alignment marks are designed to automatically provide reference information for overlay control without requiring complex external measurement and adjustment systems. The process uses self-aligned techniques where previously formed structures serve as alignment references for subsequent steps, reducing the need for complex inter-step measurements and simplifying the manufacturing process while maintaining high precision.
Data Source
AI summary
A method for fabricating a semiconductor layout includes providing a first layout having a plurality of line patterns and a second layout having a plurality of connection patterns, defining at least a first to-be-split pattern overlapping with the connection pattern among the line patterns, splitting the first to-be-split pattern at where the first to-be-split pattern overlapping with the connection pattern, decomposing the first layout to form a third layout and a fourth layout, and outputting the third layout and the further layout to a first mask and a second mask respectively.