Semiconductor Layout Stress Mitigation via Cell Density Optimization
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Solution Overview
Problem
In semiconductor integrated circuit devices with flip chip structures, stress from pads on the chip surface affects transistor performance, leading to non-uniform operating speeds and reliability issues, while existing solutions either increase costs or expand chip and package areas.
Innovation Solution
Designing the layout of semiconductor chips to prioritize cells that are not affected by timing variations under pads, such as first type cells, with higher density in internal regions below pads, and strategically arranging pads and bumps to minimize stress impact, while avoiding unnecessary increases in cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If area pads are provided on the chip surface for flip chip structure, then wire bonding is eliminated and IO cell size can be reduced, but stress from pads causes non-uniform transistor operating speeds and timing reliability degradation
Solution Approach 1:
The patent applies local quality by differentiating cell placement strategies in different regions of the chip. Specifically, timing-critical cells are excluded from regions beneath area pads where stress affects performance, while non-timing-critical cells are preferentially placed in those same regions. This localized differentiation resolves the contradiction by protecting timing reliability in stress-sensitive areas while maintaining overall device complexity benefits of flip chip structure.
Solution Approach 2:
The patent implements preliminary action by performing stress-aware cell placement during the design stage, before manufacturing. The layout synthesis tool proactively identifies timing-critical cells and prevents their placement in stress-affected regions beneath area pads. This advance planning ensures timing reliability is built into the design rather than addressed as a post-manufacturing issue, resolving the reliability concern while maintaining flip chip complexity advantages.
2Ease of manufacture
If IO cells are provided at periphery for wire bonding, then chip can be connected to package, but chip area increases due to IO cell size requirements for crimping strength
Solution Approach 1:
The patent applies the extraction principle by removing the constraint that requires large IO cells at the chip periphery. By eliminating wire bonding and replacing it with area pads for flip chip structure, the patent extracts the problematic IO cell crimping requirement from the design. This allows IO cells to be smaller since they no longer need to provide mechanical strength for wire crimping, thereby reducing chip area while maintaining package connection capability.
3Productivity
If layout synthesis is performed to reduce area, then internal logic area can be optimized, but overall chip area cannot be reduced when IO cells determine the area
Solution Approach 1:
The patent applies extraction by removing the IO cell size constraint that previously dominated chip area calculations. By transitioning from wire bonding with large crimping-required IO cells to flip chip with smaller area pads, the patent extracts the area-determining factor from IO cell dimensions. This enables layout synthesis tools to effectively reduce overall chip area since the IO cell/ pad area is no longer a fixed lower bound that prevents further optimization.
Data Source
AI summary
The layout of an LSI is previously designed so that cells below pads which will be affected by stress are arranged so that the occurrence of a malfunction of the LSI which will be caused by the influence of stress is reduced or prevented. In addition to or instead of the cell arrangement, the arrangement of pads, bumps or the like may be adjusted.