Semiconductor Layout Structure for Sub-85nm Patterning
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Solution Overview
Problem
Conventional semiconductor manufacturing processes face challenges in achieving precise patterning and increased complexity and cost due to the need for multiple patterning techniques as feature sizes decrease below 85 nanometers, particularly in BEOL processing.
Innovation Solution
The semiconductor layout structure arranges Vcc, Vss, and signal lines in a specific pattern to maintain consistent spacing distances, simplifying the multiple patterning process and reducing complexity and cost by using a 'Vcc-Vss-the first signal line-Vss-Vcc' configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple patterning processes are used to achieve precise patterning for sub-85nm features, then manufacturing precision is improved, but device complexity and process cost increase
Solution Approach 1:
The patent segments the patterning process into distinct stages (mandrel formation, spacer deposition, mandrel removal, second spacer formation) to achieve complex patterns through simpler, sequential steps. This segmentation allows each stage to focus on a specific task, improving overall precision while managing complexity through modular process design.
Solution Approach 2:
The patent employs preliminary actions by forming mandrels and spacers in advance before final pattern transfer. The first spacers are formed around mandrels, then mandrels are removed, and second spacers are formed around the first spacers. This preliminary structuring enables precise final patterns to be achieved through controlled material deposition and removal rather than direct patterning.
2Manufacturing precision
If multiple patterning processes are used to achieve precise patterning for sub-85nm features, then manufacturing precision is improved, but process cost increases
Solution Approach 1:
The patent implements self-service mechanisms where spacers automatically form around mandrels through conformal deposition, and subsequent spacers form around previous spacers. This self-organizing behavior eliminates the need for complex alignment procedures and manual intervention, reducing process cost while maintaining high precision through the inherent self-alignment of the spacer formation process.
Solution Approach 2:
The patent changes material parameters (using different dielectric materials for mandrels and spacers, controlling deposition thickness) to achieve pattern differentiation. By controlling the thickness of spacer deposits and the removal selectivity between different materials, precise patterns are achieved through parameter control rather than complex process sequences, thereby reducing cost.
3Area of moving object
If feature sizes are decreased below 85 nanometers, then device density is improved, but existing single patterning process reaches its bottleneck
Solution Approach 1:
The patent transitions from two-dimensional planar patterning to three-dimensional spacer-based patterning. By depositing conformal spacers around mandrels and then around subsequent spacers, the process adds a vertical dimension to pattern formation. This dimensional transition enables sub-85nm features to be achieved through thickness control of deposited layers rather than relying solely on lithographic resolution limits.
Data Source
AI summary
A semiconductor layout structure includes at least a first signal line and a pair of Vss lines. The first signal line and the pair of Vss lines are extended along a first direction, and the Vss lines are arranged along a second direction. The first direction and the second direction are perpendicular to each other. The Vss lines are arranged at respective two sides of the first signal line.