Semiconductor Layout With Straight-Line Interconnects to Cut Top Wiring
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Solution Overview
Problem
The increasing complexity and integration of semiconductor devices lead to excessive use of top wirings, resulting in power loss and PnR resource loss, which degrades performance and productivity.
Innovation Solution
The semiconductor device design reduces top wiring usage by employing straight-line connection wirings that connect gate electrodes and source/drain contacts without additional top wiring, optimizing the layout to minimize power loss and PnR resource consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the structure in the semiconductor device becomes increasingly complicated and highly integrated to satisfy increasing demands for high reliability, high speed, and multi-functionality, then the performance and functionality of the semiconductor device are improved, but the use of top wirings increases excessively, resulting in power loss and PnR resource loss
Solution Approach 1:
The patent applies dimensionality change by transitioning from planar 2D wiring layouts to 3D vertical interconnect structures. Specifically, it introduces via holes that extend vertically through multiple interlayer insulating film layers to connect source/drain regions across different active patterns. This vertical 3D connection approach replaces traditional horizontal top wiring routes, reducing the extent of top wiring needed while maintaining electrical connectivity for highly integrated device structures.
Solution Approach 2:
The patent implements nesting by placing via holes within vertical projections of gate electrodes. The via holes are positioned to extend through interlayer insulating films while being spatially contained within the footprint of the gate electrode structures. This nested arrangement allows interconnect pathways to be integrated within the existing device footprint without requiring additional lateral wiring space, thereby reducing top wiring usage and associated power loss.
2Adaptability or versatility
If the structure in the semiconductor device becomes increasingly complicated and highly integrated, then multi-functionality and speed are improved, but PnR (Placement and Routing) resource loss increases
Solution Approach 1:
The patent reduces PnR resource loss by utilizing the vertical dimension for interconnections. Via holes provide direct vertical pathways through multiple layers, eliminating the need for complex lateral routing networks that would be required to achieve the same connectivity in a purely 2D layout. This dimensional transition simplifies the placement and routing resources needed for highly integrated, multi-functional device structures.
Solution Approach 2:
The patent introduces interlayer insulating films as intermediary structures that facilitate vertical connectivity. These films contain embedded via holes that act as mediators, enabling electrical connections between source/drain regions of different active patterns without requiring direct lateral wiring paths. This intermediary approach streamlines the interconnect architecture, reducing the complexity of placement and routing resources.
3Loss of energy
If straight-line connection wirings are used to connect gate electrodes and source/drain contacts without additional top wiring, then top wiring usage is reduced, but layout design complexity increases
Solution Approach 1:
The patent segments the interconnect function into distinct vertical components: source/drain contacts, via holes extending through interlayer insulating films, and gate electrodes. This segmentation allows each component to be independently optimized and positioned, with via holes providing direct vertical connections that eliminate the need for additional top wiring segments. The segmented structure achieves straight-line connectivity while managing layout complexity through modular component design.
Data Source
AI summary
A semiconductor device includes a first and second active pattern extending in a first direction on a substrate, a first and second gate electrode extending in a second direction to intersect the first and second active pattern, a first source/drain contact extending in the second direction and connected to a first and source/drain region of the first and second active patterns, respectively, a first source/drain via connected to the first source/drain contact, a first cell separation film extending in the second direction and crosses the first active pattern and the second active pattern, between the first source/drain contact and the second gate electrode, a first gate via connected to the second gate electrode and arranged with the first source/drain via along the first direction, and a first connection wiring which extending in the first direction and connects the first source/drain via and the first gate via.