Semiconductor Layout Modification Using Triggered Constraint Regions
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Solution Overview
Problem
Current semiconductor layout modification methods, particularly 2-D compaction, face challenges with excessive constraints leading to computational inefficiencies and sub-optimal results due to splitting optimization problems into independent dimensions, resulting in unpredictable neighbor relationships and increased complexity with large chip designs.
Innovation Solution
A method that uses a set of proximities and triggers to generate constraints, focusing on direct neighbor relationships and design rules, allowing for efficient 2-D layout modification by maintaining a reasonable number of constraints, and iteratively adapting these constraints to optimize layout configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If 2-D compaction method is used to allow horizontal, vertical and diagonal constraints, then layout modification flexibility is improved, but the number of constraints becomes quadratic in the number of layout objects making the problem too large for computers and memories
Solution Approach 1:
The patent segments the constraint generation process by introducing triggers that divide the layout into regions. Only layout objects within the same triggered region generate constraints with each other, rather than all objects generating constraints with all other objects. This segmentation reduces the constraint complexity from quadratic to linear while maintaining 2-D modification flexibility.
Solution Approach 2:
The patent performs preliminary action by pre-identifying triggered regions and determining which layout objects fall within each region before generating constraints. This preliminary classification allows the system to efficiently determine constraint relationships without examining all object pairs, reducing computational complexity while preserving design flexibility.
2Device complexity
If 1-D compaction is used to simplify the optimization problem, then computational complexity is reduced, but the modification result becomes sub-optimal because the problem is split into two independent optimization problems
Solution Approach 1:
The patent transitions from 1-D to 2-D constraint formulation by introducing diagonal constraints and allowing simultaneous horizontal and vertical modifications within triggered regions. This dimensional expansion enables the solver to consider both dimensions together, achieving optimal 2-D layout configurations while maintaining computational tractability through region-based constraint reduction.
3Measurement precision
If all pairs of layout objects are constrained to predict neighbor relationships in 2-D compaction, then neighbor prediction accuracy is improved, but the number of constraints becomes too large for large chip designs
Solution Approach 1:
The patent applies local quality by making constraint generation context-dependent through triggered regions. Instead of uniformly constraining all object pairs, the system selectively generates constraints only for objects within the same triggered region. This local constraint application maintains accurate neighbor relationship prediction where needed while avoiding unnecessary constraints elsewhere, improving computational efficiency for large chip designs.
Data Source
AI summary
A method of modification of a semiconductor layout is provided. The layout comprises objects of semiconductor material with corners and edges. The method comprises a step of receiving (61) a set of proximities, triggers and design rules, the proximities indicating relations between neighboring edges and/or corners, the triggers defining boundaries for the modification within which boundaries the proximities are valid, the design rules describing physical requirements for the semiconductor layout. The method further comprises a step of generating (62) a set of constraints, based on the received proximities, triggers and design rules, each constraint in the set of constraints defining a limit within which the semiconductor layout may be modified without changing the proximities. Then the set of constraints to obtain a modified semiconductor layout is solved (63).