Semiconductor Layout Verification Using Virtual Patterns
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Solution Overview
Problem
As semiconductor devices are scaled down, there are technical limits to how fine patterns can be made, leading to potential defects like bridges when fabricating semiconductor integrated circuits, which existing methods fail to effectively predict and prevent.
Innovation Solution
A method and system for verifying and correcting semiconductor integrated circuit layouts by identifying predicted defect points and adjacent patterns, using virtual patterns to connect potentially floating patterns and performing design rule checks to prevent defects during the patterning process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If patterns are made finer to increase device integration, then device integration is improved, but manufacturing precision deteriorates due to technical limits of fabrication processes causing defects like bridges
Solution Approach 1:
The patent applies preliminary action by predicting defect locations before actual fabrication occurs. The system analyzes the pattern layout in advance, identifies predicted defect points where bridges may form, and generates virtual patterns at these locations. This pre-analysis and pre-correction approach allows the manufacturing process to proceed with adjusted patterns that prevent defects, thereby maintaining high integration while improving manufacturing precision.
2Reliability
If existing verification methods are used, then verification speed is maintained, but reliability deteriorates because defects cannot be effectively predicted and prevented
Solution Approach 1:
The patent introduces virtual patterns as an intermediary element between the original pattern layout and the final manufactured pattern. These virtual patterns are generated at predicted defect points and serve as mediators to prevent actual defects during fabrication. The verification module uses these virtual patterns to identify adjacent patterns that may be affected, enabling more accurate defect prediction while maintaining a manageable verification process through automated analysis.
3Manufacturing precision
If pattern layouts are corrected after fabrication, then defect correction is possible, but loss of time increases due to rework and reduced productivity
Solution Approach 1:
The patent implements preliminary correction by identifying and addressing potential defects before fabrication occurs. The verification module analyzes the pattern layout, predicts defect points, and generates corrected patterns with virtual patterns integrated into the layout prior to manufacturing. This pre-correction eliminates the need for time-consuming post-fabrication rework, thereby improving pattern accuracy while minimizing time loss.
Data Source
AI summary
An integrated circuit of a semiconductor device is fabricated by forming patterns on a wafer in conformance with a layout of the patterns. A method for verifying the layout includes providing a virtual pattern on a predicted defect point in the layout, and identifying at least one pattern from among those of the layout using the virtual pattern. The predicted defect point corresponds to a weak point where it is determined in advance that a defect will occur when the layout is transcribed on a wafer. The identified pattern is a pattern that is adjacent to the virtual pattern in the layout.