Semiconductor Circuit Layout for Thermal Warpage Relief
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Solution Overview
Problem
Ceramic circuit substrates in semiconductor devices warp and crack due to thermal stress, leading to reduced reliability, as they cannot follow the warpage of the cooling base board caused by differing linear expansion coefficients.
Innovation Solution
A semiconductor device design with a specific layout of semiconductor chips and circuit patterns on a cooling base board, including high, intermediate, and low potential circuit patterns, and a control circuit pattern arranged to straddle the center line, forming a U-shaped portion around the high potential chip mounting region, which helps distribute stress evenly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the cooling base board is fastened to the mounting area, then the semiconductor device is securely mounted, but stress concentrates in the warped portion causing ceramic circuit substrates to crack
Solution Approach 1:
The circuit substrate is designed with an asymmetric layout where the control circuit pattern straddles the center line of the cooling base board. This asymmetric positioning allows the substrate to accommodate warpage differently across its surface, reducing stress concentration at specific points while maintaining secure mounting through the fastened base board.
Solution Approach 2:
The control circuit pattern is specifically positioned to straddle the center line, creating a localized structural feature that provides flexibility in the high-stress central region. This local quality modification allows the substrate to follow warpage without cracking, while other regions maintain their structural integrity for secure mounting.
2Temperature
If ceramic circuit substrates are disposed on the cooling base board, then heat dissipation is achieved, but the substrates cannot follow warpage due to linear expansion coefficient differences causing cracks
Solution Approach 1:
The control circuit pattern is designed with specific geometric parameters and positioning that allow it to accommodate thermal expansion and contraction. By straddling the center line, the pattern creates a structural configuration that can flex with thermal warpage, enabling the substrate to follow cooling base board deformation without cracking while maintaining heat dissipation functionality.
Solution Approach 2:
The circuit substrate is functionally segmented into different potential regions (high, intermediate, low potential) with the control circuit pattern positioned centrally. This segmentation allows different regions to respond differently to thermal stress, with the central control pattern providing flexibility while other regions maintain structural stability for heat dissipation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design mitigates thermal stress, preventing warpage and cracking of ceramic circuit substrates, thereby enhancing the reliability and longevity of the semiconductor device.
Implementation Method 1
Heat from the semiconductor chips is transferred to the ceramic circuit substrates and is then dissipated from the cooling base board. Thereby, the semiconductor chips are cooled.
Implementation Method 2
when heat is generated by the semiconductor chips, the ceramic circuit substrates and cooling base board warp due to a difference in linear expansion coefficient
Data Source
AI summary
A semiconductor device includes a cooling base board and an insulated circuit substrate. On a front surface of an insulated board on the insulated circuit substrate, a high potential circuit pattern on which a semiconductor chip is mounted, an intermediate potential circuit pattern on which a semiconductor chip is mounted, a low potential circuit pattern, and a control circuit pattern are disposed so as to straddle a center line of the cooling base board. The intermediate potential circuit pattern includes a second chip mounting region, an output wiring connection region and an interconnect wiring region that form a U-shaped portion in which the high potential circuit pattern having a semiconductor chip thereon is disposed. The control circuit pattern is disposed so as to straddle the center line and faces the opening of the U-shaped portion.