Semiconductor Wiring Layout Using LCM Pitch Ratios for Dense Routing
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Solution Overview
Problem
The increasing complexity and integration of semiconductor devices require improved wiring density to enhance performance and functionality, while existing layouts struggle to efficiently pack wirings in limited areas without compromising reliability and manufacturing costs.
Innovation Solution
The semiconductor device employs a specific wiring layout where different types of wirings are spaced apart by distinct pitches, with ratios such as 6:4 and 5:4 between gate and other wirings, allowing for optimal packing density by using simulations to determine the least common multiples of these pitches, thereby maximizing the number of wirings within a limited area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If wirings are placed closer together to increase wiring density, then the number of wirings per unit area increases, but manufacturing precision and reliability deteriorate due to process variability and design rule violations
Solution Approach 1:
The patent applies parameter changes by systematically varying pitch ratios between different wiring layers (e.g., 6:5, 7:5, 8:5, 9:5, 10:9) to find optimal configurations that maximize wiring density while maintaining manufacturability. This involves changing the dimensional parameters of the wiring layout to achieve better packing efficiency without violating design rules or exceeding process capabilities.
Solution Approach 2:
The patent employs dynamic simulation and optimization to determine the least common multiple (LCM) of different pitch values, allowing the layout to adapt to process variations. By using LCM-based pitch relationships, the design dynamically adjusts to accommodate manufacturing tolerances while maintaining high wiring density, rather than using fixed rigid pitch values.
2Quantity of substance
If multiple wiring layers are stacked vertically to increase density, then wiring capacity increases, but design complexity and difficulty of detecting and measuring pitch relationships worsen
Solution Approach 1:
The patent segments the multi-layer wiring layout into modular units based on least common multiple (LCM) relationships between pitches. Each layer's pitch is divided into discrete units (e.g., 6 units for gate pitch, 5 units for first wiring pitch when ratio is 6:5), creating repeatable modular patterns that simplify design and verification while enabling high vertical integration.
Solution Approach 2:
The patent creates universal pitch ratio relationships (such as 6:5, 7:5, 8:5, 9:5, 10:9) that can be applied across different wiring layers and device types. These universal ratios serve multiple functions: they maximize wiring density, ensure LCM compatibility between layers, and provide a standardized framework that simplifies design rules and verification processes across the entire device.
3Quantity of substance
If non-standard pitch ratios are used to optimize wiring density, then wiring packing efficiency improves, but ease of manufacture worsens due to increased process difficulty
Solution Approach 1:
The patent systematically explores and validates specific pitch ratio parameters (6:5, 7:5, 8:5, 9:5, 10:9) to identify optimal values that balance packing efficiency with manufacturability. Through simulation and analysis, the patent determines which parameter combinations achieve high wiring density while remaining compatible with standard semiconductor fabrication processes and design rule checks.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a first-direction plurality of wirings extending in a first direction, and a second-direction plurality of wiring extending in a second direction intersecting the first direction. The first-direction plurality of wirings that extend in the first direction includes gate wirings spaced apart from each other in the second direction by a gate pitch, first wirings above the gate wirings spaced apart from each other in the second direction by a first pitch, second wirings above the first wirings spaced apart from each other in the second direction by a second pitch, and third wirings above the second wirings spaced apart from each other in the second direction by a third pitch. A ratio between the gate pitch and the second pitch is 6:5.