Semiconductor Package Lead Frame Clip Structure
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Solution Overview
Problem
Conventional semiconductor packaging methods are costly due to the use of gold wires and time-consuming wire bonding processes, and they are not suitable for smaller chip sizes as they require space for the wiring machine, limiting their applicability.
Innovation Solution
A semiconductor package and method that eliminates the need for wires by using a substrate lead frame, clip lead frame, and molding compound to electrically connect IC chips without gold wires, allowing for a more compact design suitable for smaller chip sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gold wires are used for connecting lead frame and chip, then electrical connection reliability is improved, but material cost increases
Solution Approach 1:
The patent replaces expensive gold wires with copper wires that are coated with a protective layer. The copper wires are cheaper material that can be disposed of after use in the packaging process, achieving cost reduction while maintaining connection functionality through the protective coating
Solution Approach 2:
The patent introduces a protective coating as an intermediary layer on the copper wires. This coating serves as a mediator that protects the copper wire from oxidation and degradation, enabling the use of cheaper copper material while maintaining the reliability that would otherwise require gold
2Reliability
If wire bonding process is used to connect lead frame and chip, then electrical connection is achieved, but processing time increases
Solution Approach 1:
The patent performs preliminary actions by pre-forming connection structures on the lead frame before chip mounting. The lead frame is prepared with pre-formed copper wire connections and protective coatings in advance, so that when the chip is mounted, the electrical connections are already in place, eliminating the need for time-consuming post-mounting wire bonding operations
Solution Approach 2:
The patent merges multiple separate processes into a single integrated process. The lead frame preparation, wire connection, and protective coating formation are combined into one unified manufacturing step that occurs before chip mounting, thereby reducing the total number of processing steps and overall manufacturing time
3Ease of manufacture
If space is reserved for wiring machine movement, then wire bonding process is feasible, but space between wires cannot be narrowed
Solution Approach 1:
The patent performs preliminary formation of connection structures on the lead frame before chip mounting. By pre-forming the copper wire connections and protective coatings on the lead frame in advance, the need for post-mounting wire bonding equipment is eliminated, allowing much tighter spacing between connection points that would be impossible with conventional wiring machines
Solution Approach 2:
The patent extracts the wire bonding operation from the manufacturing process by pre-forming all necessary electrical connections on the lead frame before chip mounting. This removes the requirement for wiring machine access and movement space, enabling compact designs with minimal spacing between connection points
4Reliability
If conventional packaging method is used, then electrical connection is achieved, but chip size cannot be reduced below certain level
Solution Approach 1:
The patent performs preliminary formation of all electrical connection structures on the lead frame before chip mounting. By pre-forming copper wire connections, protective coatings, and connection geometries in advance, the method enables support for much smaller chip sizes that would be impossible with conventional post-mounting wire bonding approaches
Solution Approach 2:
The patent merges the lead frame preparation and electrical connection formation into a single integrated process that occurs before chip mounting. This unified approach eliminates the need for subsequent wire bonding operations, enabling the use of significantly smaller chips that would not have sufficient space for conventional wiring machine access
Data Source
AI summary
A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.