Semiconductor Lead Frame Stepwise Tip Shortening for Wire Sweep Prevention
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Solution Overview
Problem
In semiconductor devices, particularly RF modules, the high impedance of wire bonding technology limits signal transmission speed and reliability due to the length of wires, which also leads to manufacturing yield issues caused by wire sweep during resin molding, resulting in short circuits between adjacent leads.
Innovation Solution
The semiconductor device design features a lead frame with stepwise shorter chip-side tip end portions of leads, allowing for shorter wire lengths and larger distances between wires, preventing short circuits and improving yield, while maintaining reliability and signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wire bonding technology is used to connect semiconductor chip and leads, then manufacturing cost is reduced compared to flip-chip bonding, but wire impedance increases and signal transmission speed decreases
Solution Approach 1:
The patent applies local quality by making the wire bonding structure different at different locations. Specifically, the chip-side tip end portions of leads are positioned at different distances from the semiconductor chip depending on their location - leads adjacent to edges have shorter distances while other leads have longer distances. This localized variation optimizes signal transmission speed for critical paths while maintaining cost-effective wire bonding for other connections.
2Ease of manufacture
If wire length is increased to accommodate normal bonding region requirements, then ease of wire bonding is improved, but impedance component increases and reliability deteriorates
Solution Approach 1:
The patent resolves this contradiction by utilizing the spatial dimension - specifically, by adjusting the positional relationship between leads and the semiconductor chip in the planar direction. The chip-side tip end portions of leads are arranged at different distances from the chip, creating varied wire lengths that balance bonding ease with impedance control. This dimensional arrangement allows shorter wires for critical signal paths while providing sufficient length for reliable bonding elsewhere.
3Speed
If tip end portion of lead is brought closer to semiconductor chip to shorten wire length, then impedance component is reduced and signal transmission speed is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies segmentation by dividing the lead array into different groups based on their positional relationships with the semiconductor chip. Leads adjacent to edges are positioned with shorter distances to the chip, while other leads have longer distances. This segmented arrangement allows optimization of signal transmission for critical paths without requiring uniform high-precision positioning for all leads, thereby reducing overall manufacturing precision requirements.
4Ease of manufacture
If leads are arranged with larger spacing to accommodate bonding region requirements, then ease of wire bonding is improved, but device area increases
Solution Approach 1:
The patent applies local quality by varying the spacing and positioning of leads based on their specific functions and locations. Leads adjacent to edges are positioned closer to the semiconductor chip with shorter bonding regions, while other leads maintain larger spacing for easier bonding. This localized differentiation allows compact overall device area while ensuring adequate bonding space where required.
Data Source
AI summary
A wire short-circuit defect during molding is prevented. A semiconductor device has a tab, a plurality of leads arranged around the tab, a semiconductor chip mounted over the tab, a plurality of wires electrically connecting the electrode pads of the semiconductor chip with the leads, and a molded body in which the semiconductor chip is resin molded. By further stepwise shortening the chip-side tip end portions of the leads as the first edge or side of the principal surface of the semiconductor chip goes away from the middle portion toward the both end portions thereof, and shortening the tip end portions of those of first leads corresponding to the middle portion of the first edge or side of the principal surface which are adjacent to second leads located closer to the both end portions of the first edge or side, the distances between second wires connected to the second leads and the tip end portions of the first leads adjacent to the second leads can be increased. As a result, it is possible to prevent the wire short-circuit defect even when wire sweep occurs due to the flow resistance of a mold resin.