Semiconductor Lead Groove Tin Block for Cut-Surface Solder Coverage

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Solution Overview

Problem

Traditional semiconductor packaging methods result in insufficient soldering around leads due to uneven tinning, failing to meet automotive and AOI detection standards.

Innovation Solution

A manufacturing method involving pre-molding packaging of lead frames, forming grooves in outer leads, filling with solder paste, and reflowing to create a tin block that exposes on the side away from the base island, ensuring sufficient solder coverage during assembly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If traditional electroplating process is used to form tin-plated layer on base island and lead back surface, then tin plating can be achieved, but the cutting surface of lead has almost no tinning resulting in insufficient solder around the lead

Engineering Contradiction:
Improvetinning coverageVSAvoidsolder sufficiency
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies preliminary action by forming a tin block in the groove before cutting the lead frame. The tin block is prepared in advance and positioned in the groove formed on the outer lead, ensuring that when the lead frame is cut and separated, the cutting surface already has sufficient tin coverage. This preliminary tin placement solves the problem of insufficient solder on cutting surfaces without requiring additional electroplating of the entire lead frame.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies local quality by concentrating the tin block specifically in the groove region on the outer lead, rather than uniformly plating the entire lead frame. This localized approach ensures that the critical cutting surface and surrounding areas have adequate tin for soldering, while avoiding unnecessary tin deposition on other areas. The groove structure itself provides localized containment for the tin block.

Inventive Principle:
Principle #3Local quality

2Reliability

If the front surface of outer lead is removed to form groove for solder paste filling, then sufficient solder can be achieved, but the structure becomes more complex

Engineering Contradiction:
Improvesolder coverageVSAvoidlead frame structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the lead frame structure into distinct functional regions: the groove formed on the outer lead, the tin block placed within the groove, and the surrounding lead structure. This segmentation allows the tin block to be independently positioned and contained within the groove, ensuring proper solder distribution while maintaining clarity in the overall structure. The groove itself segments the lead surface to create a dedicated solder receptacle.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method ensures all-position soldering from the front surface to side and back surfaces, enhancing circuit reliability and AOI detection pass rates while reducing power consumption.

Implementation Method 1

forming the tin block by reflowing solder paste after the groove is filled with the solder paste

Methodology Applied
Scientific EffectReflow:

Implementation Method 2

forming the tin block by reflowing solder paste

Methodology Applied
Scientific EffectMelting: Melting

Implementation Method 3

the tin block on the outer lead is melted during soldering, and the side of the partially melted tin block away from the base island is connected to the tin-plated layer on the back surface of the lead

Methodology Applied
Scientific EffectMelting: Melting

Data Source

PatentUS20230411252A1Manufacturing method of semiconductor packaging member, semiconductor packaging member and mounting method thereof
Publication Date: 2023.12.21 JCET SEMICON (SUQIAN) CO LTD
  • US20230411252A1 patent drawing
  • US20230411252A1 patent drawing
  • US20230411252A1 patent drawing

AI summary

The present invention provides a manufacturing method of a semiconductor packaging member, a semiconductor packaging member and a mounting method thereof. The manufacturing method includes the following steps of: pre-molding packaging a lead frame, forming a pre-molding package body both between a lead and a base, and between two adjacent leads in each lead frame unit; forming a groove by thinning an outer lead from a front surface of the outer lead; forming a tin block in the groove; mounting a chip on the base island; plastic-packaging the lead frame which has completed the wire-bonded; forming a semifinished product by forming a tin-plated layer in an exposed region of a back surface of the plastic-packaged lead frame; and forming a single semiconductor packaging member by cutting the semifinished product, the tin block in the semiconductor packaging member is exposed away from the base island.