Semiconductor Lead Integrated Island Multi-Level Structure
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Solution Overview
Problem
The existing semiconductor devices with non-lead packages face challenges in reducing the plane area of the resin package while maintaining sufficient wire stretching intervals between the pad and lead, leading to reduced accuracy in wire bonding and increased material costs due to excessive wire length.
Innovation Solution
The semiconductor device design includes a resin package with a semiconductor chip bonded to a lead integrated island, where the chip is positioned one-sided to the pad connecting terminal, allowing for satisfactory wire stretching and reduced plane area, with features like grooves on the lead integrated island to prevent conductive bonding agent seepage and alignment marks for accurate pad recognition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the lead is positioned closer to the island to reduce package area, then the plane area of the resin package is reduced, but the wire stretching interval becomes insufficient leading to poor wire bonding quality
Solution Approach 1:
The lead is configured with a multi-level structure including a lead body at a first level and a pad connecting terminal at a second level lower than the first level. This vertical dimensionality change allows the lead to occupy less horizontal space on the island while maintaining sufficient wire stretching interval, thereby reducing the plane area of the resin package without compromising wire bonding accuracy
Solution Approach 2:
The lead is divided into distinct segments: a lead body portion and a pad connecting terminal portion. This segmentation allows each part to be optimally positioned at different levels, with the lead body at the first level and the pad connecting terminal at the second level, enabling compact packaging while preserving wire bonding capabilities
2Manufacturing precision
If the wire stretching interval is increased to improve wire bonding accuracy, then the wire bonding quality is improved, but the plane area of the resin package increases
Solution Approach 1:
By utilizing the vertical dimension with the lead body at a first level and pad connecting terminal at a second level, the invention creates sufficient wire stretching interval without increasing the horizontal plane area of the resin package, thus achieving both wire bonding accuracy and compact packaging
3Adaptability or versatility
If the semiconductor chip is made larger to improve functionality, then the chip performance is improved, but the package area increases
Solution Approach 1:
The multi-level lead structure allows for optimized space utilization, enabling larger semiconductor chips to be mounted on the island without proportionally increasing the overall package area, as the lead occupies vertical space rather than horizontal space
Data Source
AI summary
A semiconductor part includes a resin package and an exposed portion exposed from a bottom surface of the resin package. The exposed portion has a first diagonal line perpendicular to both first and third sides of the package as viewed from the bottom surface. The exposed portion also has a second diagonal line perpendicular to both the second fourth side in the bottom view. A first lead terminal portion opposes the exposed portion and has a first shape in the bottom view. A second lead terminal portion, also opposing the exposed portion, has a second shape in the bottom view. A third lead terminal portion opposing the exposed portion, also has the second shape in the bottom view. A fourth lead terminal portion, similarly opposed to the exposed portion, likewise has the second shape in the bottom view.