Semiconductor Lead Mount Layout for Solder Crack Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Stress in the solder bonding mount portions of semiconductor devices can cause cracking or peeling, leading to mounting strength issues.
Innovation Solution
The semiconductor device design includes outer reverse-surface mount portions with larger areas than inner portions, positioned at the outermost positions, to distribute thermal stress evenly and prevent cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform mount portions are used for all leads, then manufacturing is simple, but thermal stress concentrates at outer mount portions causing cracking
Solution Approach 1:
The patent applies local quality by making the outer reverse-surface mount portions larger in area than the inner mount portions. This non-uniform configuration specifically addresses the stress concentration problem at outer locations while maintaining uniformity where it is not needed, thereby improving reliability without excessive complexity
Solution Approach 2:
The patent introduces asymmetry in the mount portion design by deliberately making outer mount portions larger than inner ones. This asymmetric configuration counteracts the asymmetric stress distribution that occurs during thermal cycling, preventing cracking at the more vulnerable outer locations
2Reliability
If outer mount portions are made larger to distribute stress, then cracking is prevented, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the mount portions into different size categories (outer vs. inner) with clearly defined area relationships. This segmentation allows for standardized manufacturing processes that can accommodate the size variations while maintaining sufficient precision through established fabrication techniques
Data Source
AI summary
A semiconductor device includes a plurality of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin covering the semiconductor element and a part of each lead. The sealing resin includes a first edge, a second edge perpendicular to the first edge, and a center line parallel to the first edge. The reverse surfaces of the respective leads include parts exposed from the sealing resin, and the exposed parts include an outer reverse-surface mount portion and an inner reverse-surface mount portion that are disposed along the second edge of the sealing resin. The inner reverse-surface mount portion is closer to the center line of the sealing resin than is the outer reverse-surface mount portion. The outer reverse-surface mount portion is greater in area than the inner reverse-surface mount portion.