Semiconductor Package Lead Pad Layout for Bonding Strength
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high performance and quality due to limitations in package structure design, particularly in surface mount type packages like MAP and QFN, which affect the integration and functionality of semiconductor chips.
Innovation Solution
A semiconductor device design featuring a semiconductor element with main surface electrodes, a die pad, leads, connecting members, and a resin member, where the leads overlap with the resin member and have distinct pad surfaces, with the first lead having a larger pad surface than the second lead, enhancing electrical connectivity and protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all leads have the same pad surface size, then the manufacturing process is simple and consistent, but the electrical connectivity and current carrying capacity cannot be optimized for different functional requirements
Solution Approach 1:
The patent applies local quality by making different leads have different pad surface sizes according to their specific functional requirements. First leads have larger pad surfaces for higher current carrying capacity and stronger bonding, while second leads have smaller pad surfaces for lower current applications. This localized differentiation optimizes electrical connectivity and mechanical strength for each lead's specific role without unnecessarily complicating the overall device structure.
2Reliability
If the package structure uses uniform design for all leads, then the manufacturing precision is easier to maintain, but the performance and quality of the semiconductor device cannot be enhanced
Solution Approach 1:
The patent implements local quality by differentiating pad surface sizes across different leads. First leads are fabricated with larger pad surfaces requiring higher precision control, while second leads use smaller pad surfaces with relaxed precision requirements. This approach enhances overall device quality and performance by optimizing each lead's electrical and mechanical properties according to its specific functional demands.
3Strength
If the pad surface area is increased for better bonding, then the bonding strength is improved, but the area occupied on the wiring board increases, reducing mounting density
Solution Approach 1:
The patent applies local quality by assigning different pad surface sizes to different leads based on their specific bonding requirements. First leads that require stronger bonding have larger pad surfaces, while second leads with lower bonding requirements have smaller pad surfaces. This differentiated approach optimizes bonding strength for each lead's functional needs while minimizing the overall package footprint, thereby maintaining high mounting density on wiring boards.
Solution Approach 2:
The patent implements partial action by providing larger pad surfaces only for first leads that require stronger bonding, rather than uniformly enlarging all leads. This selective approach ensures adequate bonding strength where needed while keeping the overall package size compact, enabling high-density surface mounting without compromising essential bonding requirements.
Data Source
AI summary
A semiconductor device includes: a semiconductor element having an element main surface and an element back surface spaced apart from each other in a thickness direction and including a plurality of main surface electrodes arranged on the element main surface; a die pad on which the semiconductor element is mounted; a plurality of leads including at least one first lead and at least one second lead and arranged around the die pad when viewed in the thickness direction; a plurality of connecting members including a first connecting member and a second connecting member and configured to electrically connect the plurality of main surface electrodes and the plurality of leads; and a resin member configured to seal the semiconductor element, a part of the die pad, parts of the plurality of leads, and the plurality of connecting members and having a rectangular shape when viewed in the thickness direction.


