Semiconductor Leading Line Width Consistency via Sidewall Dummy Patterns

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Solution Overview

Problem

In semiconductor devices, the leading portion often has a wider space compared to the wiring portion, leading to a higher micro-loading effect that results in thinner line widths in the leading portion, which can be inconsistent with the wiring portion.

Innovation Solution

The manufacturing method involves forming core and dummy patterns in the leading and wiring portions, followed by deposition of a sidewall material and subsequent etching to create sidewall patterns and dummy patterns, which are then used as masks to transfer patterns onto the process target film, ensuring the line and space around the leading lines are equal to those in the wiring portion, thereby reducing the micro-loading effect.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the leading portion has a wider space compared to the wiring portion, then the micro-loading effect becomes high, but the line width in the leading portion becomes thinner than in the wiring portion

Engineering Contradiction:
Improveline width consistencyVSAvoidmicro-loading effect
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary action by forming a mandrel pattern and sidewall pattern before the final etching process. The mandrel pattern is formed with a first width in the leading portion and a second width in the wiring portion, and the sidewall pattern is formed with a third width in the leading portion and a fourth width in the wiring portion. This preliminary structuring allows the etching process to produce consistent line widths despite the wider space in the leading portion, effectively compensating for the micro-loading effect before the final pattern transfer.

Inventive Principle:
Principle #10Preliminary action

2Area of stationary object

If the space in the leading portion is made wider, then the micro-loading effect increases, but the line width becomes thinner and inconsistent

Engineering Contradiction:
Improvespace in leading portionVSAvoidline width consistency
Core Design Contradiction:
Area of stationary objectVSManufacturing precision

Solution Approach 1:

The patent applies local quality by making the mandrel pattern and sidewall pattern have different dimensions in different regions. Specifically, the mandrel pattern has a first width in the leading portion and a second width in the wiring portion, while the sidewall pattern has a third width in the leading portion and a fourth width in the wiring portion. This localized variation in pattern dimensions compensates for the wider space in the leading portion, ensuring that the final etched lines have consistent widths across both regions despite the different local conditions.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method effectively reduces the micro-loading effect in the leading portion, allowing the line width of the leading lines to be made equal to the wiring lines, maintaining consistency and improving manufacturing precision.

Implementation Method 1

deposition of a sidewall material and subsequent etching to create sidewall patterns

Methodology Applied
Scientific EffectPhysical vapor deposition: Physical Vapour Deposition

Implementation Method 2

subsequent etching to create sidewall patterns, which are then used as masks to transfer patterns onto the process target film

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS9087884B1Manufacturing method of semiconductor device and semiconductor device
Publication Date: 2015.07.21 KIOXIA CORP
  • US9087884B1 patent drawing
  • US9087884B1 patent drawing
  • US9087884B1 patent drawing

AI summary

According to one embodiment, a first core pattern is formed in a wiring portion on a process target film and a second core pattern, which is led out from the first core pattern and includes an opening, is formed in a leading portion on the process target film, a sidewall pattern is formed along an outer periphery of the first core pattern and the second core pattern and a sidewall dummy pattern is formed along an inner periphery of the opening of the second core pattern, the first core pattern and the second core pattern are removed, and the process target film is processed to transfer the sidewall pattern and the sidewall dummy pattern.