Semiconductor Leakage Estimation via Chip Segmentation
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Solution Overview
Problem
Current full chip leakage current estimation models, such as the lognormal leakage estimation model, face significant computational complexity issues, especially as the number of environmental factors increases, making them impractical for large-scale semiconductor device designs.
Innovation Solution
A method is introduced that divides the chip into segments, determines spatial correlations between process parameters, and generates virtual cell leakage characteristic functions through arithmetic operations, reducing computational complexity by summing lognormal distributions arithmetically rather than statistically, and applying principal component analysis to minimize spatial correlation matrix processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the lognormal leakage estimation model is used to estimate full chip leakage current, then the estimation accuracy considering all process parameters and environmental factors is improved, but the computational complexity increases geometrically
Solution Approach 1:
The patent divides the chip into multiple segments and further divides each segment into multiple regions. This segmentation allows the computational task to be distributed and managed in smaller units, reducing the geometric complexity growth while maintaining comprehensive coverage of all process parameters and environmental factors across the entire chip.
Solution Approach 2:
The patent introduces a spatial dimension by dividing the chip into segments and regions with specific spatial relationships. By organizing the estimation in a hierarchical spatial structure (chip → segments → regions), the model manages computational complexity through dimensional organization while preserving the accuracy of leakage current estimation across all factors.
2Measurement precision
If the number of environmental factors is increased to improve estimation accuracy, then the comprehensive leakage current prediction is improved, but the computational overload increases
Solution Approach 1:
By segmenting the chip and organizing environmental factors across different spatial units, the patent enables parallel processing of multiple factors without increasing sequential computational overhead. Each segment can process its local environmental factors independently, improving computational efficiency while maintaining comprehensive factor coverage.
Solution Approach 2:
The patent applies partial action by focusing computational resources on critical segments and regions where leakage current is most significant. Rather than uniformly processing all factors across the entire chip with equal detail, the model strategically allocates computational effort to areas where it provides the most value, improving overall efficiency.
Data Source
AI summary
In a method of estimating a leakage current in a semiconductor device, a chip including a plurality of cells is divided into segments by a grid model. Spatial correlation is determined as spatial correlation between process parameters concerned with the leakage currents in each of the cells. A virtual cell leakage characteristic function of a cell is generated by arithmetically operating actual leakage characteristic functions. A segment leakage characteristic function of a segment is generated by arithmetically operating the virtual cell leakage characteristic functions of all cells in the segment. Then, a full chip leakage characteristic function of the chip is generated by statistically operating the segment leakage characteristic functions of all segments in the chip. Accordingly, computational loads of Wilkinson's method for generating the full chip leakage characteristic function can remarkably be reduced.