Semiconductor Device Leakage Compensation via Dummy Cell Arrays
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Solution Overview
Problem
Semiconductor devices face accuracy issues in read operations due to leakage currents flowing through unselected memory cells, which can be exacerbated by temperature changes, affecting the reliability and performance of data reading.
Innovation Solution
The semiconductor device incorporates a configuration with multiple memory cell arrays, including reference and dummy cells, where the second column decoder connects at least one dummy cell or memory cell from an unselected array to a sense amplifier, allowing for compensation of leakage currents without separate temperature or time-dependent parameter detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple memory cell arrays with dummy cells are used for leakage compensation, then read operation accuracy is improved, but device complexity increases
Solution Approach 1:
The memory device is divided into multiple memory cell arrays (first memory cell array and second memory cell array), where each array contains memory cells, reference cells, and dummy cells. This segmentation allows the leakage current from unselected cells to be compensated by corresponding dummy cells in the other array, thereby improving read operation accuracy while managing complexity through modular organization.
Solution Approach 2:
Dummy cells are created as copies of memory cells in the opposite array. When reading from the first memory cell array, dummy cells in the second memory cell array are activated to compensate for leakage currents. This copying approach enables automatic leakage compensation without additional sensing circuitry, improving measurement precision while maintaining reasonable device complexity.
2Reliability
If dummy cells from unselected array are connected to sense amplifier, then leakage current compensation is achieved, but column decoder complexity increases
Solution Approach 1:
The column decoders are designed with multi-functionality to handle both normal read operations and leakage compensation operations. The first column decoder can connect selected memory cells from the first array to the sense amplifier, while the second column decoder simultaneously or alternatively connects dummy cells from the second array. This universal design enables the column decoders to perform multiple functions without requiring separate dedicated circuitry, thereby achieving reliability improvement while controlling complexity.
Solution Approach 2:
The column decoders dynamically reconfigure their connections based on the read operation requirements. During a read operation, the decoders can switch between connecting memory cells and connecting dummy cells to the sense amplifier. This dynamic reconfiguration allows the system to adapt to different operational modes, achieving effective leakage compensation while maintaining manageable decoder complexity through flexible resource allocation.
Data Source
AI summary
A semiconductor device includes a first memory cell array including a plurality of first memory cells, a plurality of first reference cells and a plurality of first dummy cells, a second memory cell array including a plurality of second memory cells, a plurality of second reference cells and a plurality of second dummy cells, an input/output circuit provided between the first memory cell array and the second memory cell array, a first column decoder connected between the first memory cell array and the input/output circuit and a second column decoder connected between the second memory cell array and the input/output circuit. The second column decoder connects one of the plurality of second dummy cells and the plurality of second memory cells to a selected sense amplifier of the input/output circuit, when the first column decoder connects a selected first memory cell to the selected sense amplifier.