Semiconductor Device Leakage Current Suppression via Segmented Wells
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Solution Overview
Problem
Semiconductor devices with multiple wells on a P-type semiconductor substrate experience leakage current issues when potential differences occur between N-type wells, which existing designs fail to adequately address.
Innovation Solution
A semiconductor device structure featuring an epitaxial layer with strategically placed impurity regions and wells of different conductivity types, along with MOS transistors, to suppress leakage current by controlling potential differences and using impurity regions with higher concentrations to isolate wells effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple N-type wells are provided in a P-type semiconductor substrate to support operating states, then the adaptability of the semiconductor device is improved, but leakage current occurs between the N-type wells when potential differences exist
Solution Approach 1:
The invention divides the semiconductor substrate into distinct regions by introducing P-type impurity regions between N-type wells. This segmentation creates electrical isolation zones that prevent leakage current while maintaining the ability to support multiple operating states through separate well structures.
Solution Approach 2:
P-type impurity regions are introduced as intermediary elements between N-type wells. These impurity regions act as mediators that electrically isolate adjacent N-type wells, preventing direct leakage current paths while allowing each well to independently support different operating states.
2Object-generated harmful factors
If P-type impurity regions with higher concentration are introduced between N-type wells to suppress leakage current, then leakage current is reduced, but the device complexity increases
Solution Approach 1:
The invention applies local quality by creating P-type impurity regions with specifically higher concentration only in the areas between N-type wells where leakage current is problematic. The rest of the device maintains standard doping concentrations, thus suppressing leakage without unnecessarily complicating the entire device structure.
Solution Approach 2:
The invention changes the impurity concentration parameter locally by introducing P-type impurities at concentrations higher than the base epitaxial layer. This parameter change creates effective electrical isolation zones that suppress leakage current while being implemented through standard semiconductor manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure effectively suppresses leakage current between wells, enabling miniaturization and improved design flexibility while ensuring reliable electrical separation and higher breakdown voltages for certain transistors.
Implementation Method 1
an epitaxial layer of a first conductivity type grown epitaxially on the semiconductor substrate
Implementation Method 2
the first impurity region having a higher impurity concentration than the epitaxial layer... enables the occurrence of leakage current between the first well and the second well to be suppressed
Data Source
AI summary
A semiconductor device according to the invention includes an epitaxial layer of a first conductivity type, a first well of a second conductivity type to which a first potential is applied, a second well of the second conductivity type to which a second potential that differs from the first potential is applied, a third well of the first conductivity type provided in the epitaxial layer between the first well and the second well, a first impurity region of the first conductivity type provided in the epitaxial layer under the first well, a first MOS transistor provided in the first well, a second MOS transistor provided in the second well, and a third MOS transistor provided in the third well, the first impurity region having a higher impurity concentration than the epitaxial layer.


