Semiconductor Light Emitting Device Conductive Support Planarization
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Solution Overview
Problem
Existing methods for manufacturing semiconductor light emitting devices using III-V nitride semiconductors face challenges in improving electrical characteristics, particularly in achieving reliable electrical connections and minimizing substrate removal-induced stress, which affects chip reliability and measurement accuracy.
Innovation Solution
The method involves forming a semiconductor light emitting device with a conductive support member having a planarized surface, using a channel layer as an etching stop and isolation layer, and employing a laser lift-off process for substrate removal, along with a mesa etching process to expose the channel layer, thereby enhancing adhesive strength and reducing delamination risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick metal layer is formed over epitaxial layers for electrical connection, then electrical conductivity is improved, but substrate removal-induced stress increases causing chip delamination
Solution Approach 1:
The metal layer is divided into multiple thin layers (e.g., Al layer 50 nm + Cu layer 50 nm) instead of a single thick layer. This segmentation reduces the overall stress while maintaining electrical conductivity, as each thin layer can better accommodate substrate removal stress without causing delamination.
Solution Approach 2:
The patent uses composite metal layer structures combining different materials (Al/Cu, Al/Ag, or Al/Au) with complementary properties. The Al layer provides good adhesion and electrical conductivity, while the Cu/Ag/Au layers provide additional conductivity and stress relief, creating a composite structure that balances electrical performance and mechanical strength.
2Productivity
If substrate is removed completely for device separation, then device independence is improved, but measurement precision deteriorates due to stress-induced deformation
Solution Approach 1:
A release layer (e.g., SiO2 or Si3N4) is formed on the substrate before epitaxial growth. This release layer is selectively removed to enable clean substrate separation without damaging the epitaxial layers, allowing complete substrate removal while maintaining chip integrity and measurement accuracy.
Solution Approach 2:
The release layer acts as an intermediary between the substrate and epitaxial layers during the separation process. It facilitates clean detachment by providing a separation plane, enabling complete substrate removal while preventing direct stress transmission to the chip structure that would cause deformation.
3Reliability
If multiple metal layers are formed for electrical connection, then electrical characteristics are improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies different metal materials at different locations and depths: Al layer for adhesion and conductivity, Cu/Ag/Au layers for enhanced conductivity and stress management. Each layer has optimized thickness and material properties tailored to its specific function, achieving high electrical performance without unnecessary complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the electrical characteristics and reliability of the semiconductor light emitting device by ensuring precise measurements and minimizing stress during substrate removal, leading to enhanced chip reliability and performance.
Implementation Method 1
a laser beam is irradiated to remove the substrate
Implementation Method 2
a mesa etching process to expose the channel layer
Data Source
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AI summary
Disclosed is a method of manufacturing a semiconductor light emitting device (100). The method includes forming a light emitting structure including a first conductive semiconductor layer (110), an active layer (120), and a second conductive semiconductor layer (130) on a substrate, forming an electrode layer (150) on the light emitting structure, forming a conductive support member (170) on the electrode layer, and planarizing a top surface of the conductive support member (170).