Semiconductor Level Shifter Layout for Equal Rise-Fall Timing
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Solution Overview
Problem
Conventional level shift circuits in semiconductor integrated circuits exhibit a difference in transition time at rise and fall times of input signals due to unequal PMOS and NMOS transistor activation, leading to performance degradation in external devices.
Innovation Solution
The implementation of a level shift circuit configuration with equal channel widths for corresponding PMOS and NMOS transistors in both the first and second level shifters, ensuring balanced driving abilities and minimizing the difference in transition times by cross-coupling gate and drain terminals, thereby equalizing transition times at both rise and fall.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the conventional level shift circuit configuration is used with standard PMOS and NMOS transistor arrangements, then the circuit can perform basic level shifting function, but the transition time differs between rise and fall times leading to performance degradation
Solution Approach 1:
The patent applies asymmetry by setting different channel widths for PMOS and NMOS transistors in a non-conventional arrangement. Specifically, the first PMOS transistor has a first channel width, the second PMOS transistor has a second channel width, the first NMOS transistor has a third channel width, and the second NMOS transistor has a fourth channel width, where these widths are specifically designed to balance the rise and fall transition times. This asymmetric design compensates for the inherent differences in PMOS and NMOS transistor characteristics, achieving equal transition times for both rising and falling edges of the output signal.
2Reliability
If the transition time difference between rise and fall is reduced, then external device performance is improved, but this requires precise matching of transistor parameters which increases design complexity
Solution Approach 1:
The patent employs parameter changes by systematically adjusting the channel widths of four transistors (first PMOS, second PMOS, first NMOS, second NMOS) to achieve equal transition times. The specific parameter relationships are defined as: first channel width/second channel width = fifth parameter, and third channel width/fourth channel width = sixth parameter, where the fifth and sixth parameters are determined based on the desired transition time equality. This parameter-based approach provides a systematic method to balance transition times without requiring complex design iterations.
Data Source
AI summary
According to one embodiment, a semiconductor integrated circuit includes first and second level shift circuits. The first level shifter includes a plurality of transistors and is connected to a power source voltage supply node of a first power source system and to which a first signal of a second power source system and a level inversion signal of the first signal are input. The second level shifter includes a plurality of transistors and is connected to the power source voltage supply node of the first power source system and to which the level inversion signal of the first signal of the second power source system and an output signal of the first level shifter are input. The first and second level shifters have substantially the same circuit configuration and driving abilities of corresponding ones of the transistors in the first and second level shifters are substantially set equal.