Semiconductor Package Lid With Vertical Interconnects for Compact Reliability
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Solution Overview
Problem
Conventional semiconductor packages face issues of high cost, decreased reliability, and large package sizes, leading to suboptimal performance.
Innovation Solution
A semiconductor device design comprising a substrate with a conductive structure, an electronic component electrically coupled to the substrate, a lid structure with a vertical interconnect, and a seal, which forms a compact and reliable package that provides electrical connections between external components and the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor packages are used, then manufacturing cost is reduced, but reliability decreases and package size increases
Solution Approach 1:
The patent transitions from planar interconnect layouts to three-dimensional vertical interconnect structures. Through-silicon vias (TSVs) and vertical conductors penetrate the substrate thickness direction, enabling electrical connections in the vertical dimension rather than relying solely on surface-level routing. This dimensional change reduces the lateral footprint of the package while maintaining reliable electrical connectivity.
Solution Approach 2:
The patent implements a nested structure where the lid encloses the substrate, which in turn encloses the electronic component. This nested arrangement compactly integrates multiple functional elements (component, substrate, interconnects, lid) into a hierarchical structure, minimizing overall package volume while ensuring protective enclosure and electrical connectivity.
2Ease of manufacture
If conventional semiconductor packages are used, then manufacturing simplicity is maintained, but cost increases and performance decreases
Solution Approach 1:
The patent divides the package into distinct functional modules: the electronic component, the substrate with integrated vertical interconnects, and the enclosing lid. This segmentation allows each module to be manufactured and prepared independently using optimized processes, then assembled together. The substrate module incorporates TSVs and conductors as integrated features, enabling parallel processing and improving overall manufacturing efficiency despite the advanced structure.
3Productivity
If larger package sizes are used, then manufacturing ease is improved, but performance decreases
Solution Approach 1:
The patent exploits the vertical dimension by implementing through-silicon vias and vertical conductors that extend through the substrate thickness. This allows electrical interconnects to be formed in the depth direction rather than requiring extensive lateral routing, thereby reducing the planar footprint of the package while achieving high-performance electrical connectivity between components.
Solution Approach 2:
The patent employs an asymmetric package architecture where the substrate thickness and vertical interconnect dimensions are optimized independently from lateral dimensions. The lid encloses the substrate asymmetrically, with opening configurations tailored to the specific component layout. This asymmetric design enables compact overall volume while accommodating high-density vertical interconnect structures that deliver superior electrical performance.
Data Source
AI summary
In one example, a semiconductor device comprises a substrate comprising a conductive structure, an electronic component over a top side of the substrate and electrically coupled with the conductive structure, a lid structure over the substrate and over the electronic component, and a vertical interconnect in the lid structure extending to a top surface of the lid structure and electrically coupled with the conductive structure. Other examples and related methods are also disclosed herein.