Semiconductor Light Emitting Device With Copper Heat Dissipation
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Solution Overview
Problem
Existing semiconductor light emitting devices face challenges in achieving high heat dissipation and mechanical strength while maintaining a compact size, particularly when large electric power is applied, and there is a need for cost-effective manufacturing methods that enhance productivity.
Innovation Solution
The semiconductor light emitting device features a chip with a thicker and larger package structure, incorporating a phosphor layer and metal layers with high thermal conductivity, such as copper, to facilitate heat dissipation and mechanical reinforcement, along with a manufacturing process that includes wafer-level packaging and electrolytic plating to reduce costs and improve productivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a larger outer shape of LED package is used, then heat dissipation performance is improved, but device size increases
Solution Approach 1:
The patent transitions from planar heat dissipation to three-dimensional heat dissipation by forming metal layers (particularly copper layers) with thickness greater than the chip thickness, creating vertical heat conduction paths that extend in the thickness direction. This dimensional change allows efficient heat dissipation without proportionally increasing the lateral footprint of the device.
Solution Approach 2:
The patent employs composite material structures combining different metal layers (copper layers for thermal conductivity, aluminum layers for electrical connection) with the semiconductor chip and insulating layers. This composite approach optimizes both heat dissipation and electrical functionality within a compact package volume.
2Ease of manufacture
If wafer-level packaging is implemented, then manufacturing cost is reduced, but heat dissipation capability may be compromised
Solution Approach 1:
The patent segments the manufacturing process into wafer-level batch processing for cost efficiency, while incorporating individualized heat dissipation structures (metal layers formed on each chip region) that maintain thermal performance. The copper layers are formed through wafer-level electrolytic plating, achieving both economies of scale and individual heat management.
Solution Approach 2:
The patent changes the physical parameters of the package structure by forming metal layers with thickness greater than the chip thickness, creating a three-dimensional heat dissipation architecture that maintains high thermal performance despite the cost-effective wafer-level packaging approach.
3Temperature
If metal layers with high thermal conductivity are added, then heat dissipation is improved, but device complexity increases
Solution Approach 1:
The patent designs metal layers that serve multiple functions simultaneously: copper layers provide both electrical connection and heat dissipation, while aluminum layers provide electrical connection and structural support. This multi-functionality reduces the need for separate dedicated heat dissipation components, thereby limiting complexity increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves high heat dissipation performance, mechanical strength, and cost-effectiveness by utilizing a larger package structure and advanced manufacturing techniques, enabling efficient light emission and reliable operation under high power conditions.
Implementation Method 1
incorporating a phosphor layer and metal layers with high thermal conductivity, such as copper, to facilitate heat dissipation
Implementation Method 2
a manufacturing process that includes wafer-level packaging and electrolytic plating
Data Source
Figure 1
Figure 2A~2B
Figure 3A~3C
AI summary
According to one embodiment, a semiconductor light emitting device (1a-1h), includes: a semiconductor layer (15) including a first face (15a), a second face opposite to the first face, a side face, and a light emitting layer (12a); a p-side electrode (16) provided on the second face; an n-side electrode (17) provided on the side face; a first p-side metal layer (23) provided on the p-side electrode and connected electrically with the p-side electrode; a first n-side metal layer (26) provided on the periphery of the n-side electrode and connected electrically with the n-side electrode; a first insulating layer (27) provided on a face on the second face side in the first n-side metal layer; a second p-side metal layer (29) connected with the first p-side metal layer on the first p-side metal layer, and provided, extending from on the first p-side metal layer to on the first insulating layer; and a second n-side metal layer (30) provided on a face on the second face side in the first n-side metal layer in a peripheral region of the semiconductor layer and connected electrically with the first n-side metal layer.