Semiconductor Light-Emitting Device Wafer-Level Bonding
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Solution Overview
Problem
The commercialization of semiconductor light emitting devices at the wafer level is hindered by difficulties in aligning electrode films and patterns, and the process is lengthy and costly, with challenges in removing substrates without causing cracks in semiconductor layers.
Innovation Solution
A semiconductor light emitting device is manufactured by growing semiconductor layers on a growth substrate, bonding them to a supporting substrate with electrical passes, removing the substrate, and forming electrical connections to prevent cracking and simplify alignment, using a bonded layer to connect the semiconductor layers electrically and facilitate easy electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If substrate removal is performed to enable vertical chip configuration, then device performance is improved, but cracking in semiconductor layers occurs
Solution Approach 1:
A bonded layer is introduced between the semiconductor layers and supporting substrate before substrate removal. This bonded layer acts as a cushioning element that prevents cracking in the semiconductor layers during the substrate removal process, while still allowing the device to achieve its vertical chip configuration and optimal performance
2Manufacturing precision
If electrode films and patterns are aligned at chip level, then precise electrical connections are achieved, but manufacturing complexity and time increase
Solution Approach 1:
The patent transitions from chip-level alignment to wafer-level alignment by performing electrode film formation and patterning before substrate removal. This dimensional change in the manufacturing process allows for more precise alignment using wafer-level techniques while reducing overall manufacturing complexity through batch processing
3Reliability
If substrate removal is performed to simplify device structure, then device performance is improved, but manufacturing time increases
Solution Approach 1:
The bonded layer is formed and electrical passes are created through the substrate before the substrate removal step. This preliminary action ensures that all necessary electrical connections are established in advance, allowing the substrate to be removed efficiently without extending the overall manufacturing cycle time
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the production of semiconductor light emitting devices at the wafer level with improved alignment and reduced cracking, enhancing productivity and simplifying the manufacturing process while maintaining device performance.
Implementation Method 1
an active layer interposed between the first semiconductor layer and the second semiconductor layer, generating light via electron-hole recombination
Implementation Method 2
a bonded layer, which bonds the second semiconductor layer side of the plurality of semiconductor layers to the first surface side of the supporting substrate and is electrically connected with the first electrical pass
Data Source
AI summary
The disclosed invention relates to a semiconductor light-emitting element comprising: a plurality of semiconductor layers which are provided with a growth substrate eliminating surface on the side where a first semiconductor layer is located; a support substrate which is provided with a first electrical pathway and a second electrical pathway; a joining layer which joins a first surface side of the support substrate with a second semiconductor layer side of the plurality of semiconductor layers, and is electrically linked with the first electrical pathway; a joining layer eliminating surface which is formed on the first surface, and in which the second electrical pathway is exposed, and which is open towards the plurality of semiconductor layers; and an electrical link for electrically linking the plurality of semiconductor layers with the second electrical pathway exposed in the joining layer eliminating surface.