Semiconductor Light Emitting Element Si Dopant Layering

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Solution Overview

Problem

The existing methods for manufacturing semiconductor light emitting elements face challenges in achieving high light emission power due to defects in the n cladding layer and p-type semiconductor layer, leading to reduced crystallinity and product yield, especially when a large current is applied.

Innovation Solution

A method involving the sequential formation of a regrowth layer, a second n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer in a specific dopant concentration and thickness range, with the second n-type semiconductor layer formed in two stages with varying Si concentrations, is employed to improve crystallinity and reduce resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the n-type semiconductor layer, light emitting layer, and p-type semiconductor layer are continuously formed in the same growth chamber, then the manufacturing process is simplified, but the p-type semiconductor layer cannot achieve sufficiently low resistivity due to dopant contamination from the n-type layer

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidp-type semiconductor layer resistivity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The manufacturing process is divided into two separate growth chambers: a first growth chamber for forming the n-type semiconductor layer and a second growth chamber for forming the p-type semiconductor layer. This segmentation prevents dopant contamination between layers while maintaining process efficiency, resolving the contradiction between manufacturing simplicity and layer quality.

Inventive Principle:
Principle #1Segmentation

2Reliability

If the n-type semiconductor layer and p-type semiconductor layer are formed in separate growth chambers, then the p-type layer resistivity is improved, but the output of the semiconductor light emitting element becomes insufficient

Engineering Contradiction:
Improvep-type semiconductor layer resistivityVSAvoidlight emitting element output
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

The n cladding layer is designed with a specific Si dopant concentration range (1×10^18 to 1×10^19 atoms/cm³) that is optimized for its local function of providing both low resistivity and high crystallinity. This localized optimization allows the layer to contribute to both improved reliability and higher output when a large current is applied.

Inventive Principle:
Principle #3Local quality

3Reliability

If high Si dopant concentration is used in the n cladding layer, then the resistivity is reduced, but the crystallinity is reduced leading to defects in subsequent layers

Engineering Contradiction:
Improven cladding layer resistivityVSAvoidcrystallinity of n cladding layer and subsequent layers
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The Si dopant concentration in the n cladding layer is precisely controlled within the range of 1×10^18 to 1×10^19 atoms/cm³. This parameter optimization achieves the right balance between resistivity and crystallinity, allowing the layer to provide low resistance while maintaining high crystallinity that enables defect-free growth of subsequent light emitting and p-type layers.

Inventive Principle:
Principle #35Parameter changes

4Power

If a large current is applied to improve light emission power, then the light emission power increases, but defects in the n cladding layer and p-type layer become more prominent reducing product yield

Engineering Contradiction:
Improvelight emission powerVSAvoidproduct yield
Core Design Contradiction:
PowerVSProductivity

Solution Approach 1:

The n cladding layer is formed with optimized Si dopant concentration (1×10^18 to 1×10^19 atoms/cm³) and appropriate thickness (50-200 nm) before forming the light emitting and p-type layers. This preliminary optimization of the n cladding layer ensures high crystallinity and low defect density, which provides a solid foundation that enables the device to withstand large currents and achieve high light emission power without compromising product yield.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the crystallinity and flatness of the n-type semiconductor layers, allowing for high-crystallinity growth of subsequent layers, thereby improving the product yield and light emission power, especially under high-current conditions.

Implementation Method 1

there is a method which continuously forms an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer on a substrate made of, for example, a sapphire single crystal in this order using a metal organic chemical vapor deposition method (MOCVD method)

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Data Source

PatentUS8859313B2Method for manufacturing semiconductor light emitting element, semiconductor light emitting element, lamp, electronic device and mechanical apparatus
Publication Date: 2014.10.14 TOYODA GOSEI CO LTD
  • US8859313B2 patent drawing
  • US8859313B2 patent drawing
  • US8859313B2 patent drawing

AI summary

A method for manufacturing a semiconductor light emitting element (1) which includes a first step of forming a first n-type semiconductor layer (12c) on a substrate (11) and a second step of sequentially forming a regrowth layer (12d) of the first n-type semiconductor layer (12c), a second n-type semiconductor layer (12b), a light emitting layer (13), and a p-type semiconductor layer (14) on the first n-type semiconductor layer (12c). In the step of forming the second n-type semiconductor layer (12b), a step (1) of supplying Si less than that forming the regrowth layer (12d) as a dopant to form a first layer of the second n-type semiconductor layer and a step (2) of supplying the Si more than that in the step (1) to form a second layer of the second n-type semiconductor layer are performed in this order.