Semiconductor Device with Light-Activated Gate for Low-Power Optical Clocking
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Solution Overview
Problem
Existing semiconductor devices for optoelectric hybrid LSIs face high power consumption due to current-based optoelectric conversion in optical clocking, and lack a mechanism to eliminate accumulated optical carriers, making it difficult to turn off the CMOS.
Innovation Solution
A semiconductor device comprising n-type and p-type MOS transistors connected in series, with a first gate extending above their channels, using light to generate electrons and holes that pass through the channels, allowing for reliable switching and efficient optoelectric conversion with reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If current-based optoelectric conversion is used in optical clocking, then fast optical clocking is enabled, but very high power consumption occurs
Solution Approach 1:
The patent replaces the conventional current-based optoelectric conversion mechanism with a voltage-based mechanism. Specifically, it substitutes the photodiode-current-CMOS control chain with a photodiode-voltage-MOS transistor channel control chain, where optically generated carriers directly modulate the gate voltage of the MOS transistor, thereby switching the transistor on and off. This substitution fundamentally changes the energy conversion pathway from current-driven to voltage-driven, resolving the high power consumption issue while maintaining fast optical clocking capability.
2Use of energy by moving object
If voltage conversion of light is used to reduce power consumption, then power consumption is reduced, but the CMOS cannot be turned off due to accumulated optical carriers
Solution Approach 1:
The patent applies the inversion principle by using a p-type MOS transistor in addition to the n-type MOS transistor. The p-type MOS transistor responds to holes (positive carriers) while the n-type responds to electrons (negative carriers). By inverting the carrier type sensitivity, the system can effectively reset the gate voltage: when electrons accumulate to turn on the n-type MOS, holes subsequently arrive to turn off the p-type MOS, thereby clearing the accumulated charge and enabling reliable switching cycles. This dual-transistor approach with inverted carrier responses solves the problem of incomplete switching.
3Use of energy by moving object
If a photodiode is connected to the gate of a CMOS for voltage conversion, then power consumption is reduced, but no mechanism exists for eliminating accumulated optical carriers
Solution Approach 1:
The patent makes the gate structure universal by extending it to serve dual purposes: the first gate region handles electron-generated signals for n-type MOS control, while the same gate structure also responds to hole-generated signals for p-type MOS control. This multi-functional gate design eliminates the need for separate carrier elimination mechanisms, as the gate itself participates in both turning on and turning off the transistor pair through its response to both electron and hole carriers generated by the photodiode.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables high-speed optical clocking with low power consumption by effectively switching the CMOS transistors using holes or electrons generated by the first gate, achieving reliable operation and reduced power usage.
Implementation Method 1
by providing light to the first gate, electrons and holes being generated
Data Source
AI summary
A semiconductor device includes: an n-type MOS transistor and a p-type MOS transistor connected in series; and a first gate extending via an insulating film above a channel of the n-type MOS transistor and a channel of the p-type MOS transistor. By providing light to the first gate, electrons and holes are generated, at least one of either of the electrons and holes passes through above the channel of the n-type MOS transistor and at least one of the either of the electrons and holes passes through above the channel of the p-type MOS transistor, whereby the n-type MOS transistor and the p-type MOS transistor are switched.