Semiconductor Device Line-End Biasing Bridge Risk
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Solution Overview
Problem
Semiconductor devices face challenges in achieving higher integration, reliability, and multi-functionality due to process risks associated with bridge risk regions during manufacturing, leading to potential electrical shorts and defects.
Innovation Solution
A method of manufacturing semiconductor devices that involves providing a layout with specific patterns, examining bridge risk regions, and performing line-end biasing to adjust the layout patterns, thereby reducing the risk of electrical shorts by spacing out extensions of conductive patterns to prevent bridge formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If line-end biasing is performed to prevent bridge formation, then reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by performing line-end biasing during the layout design stage before manufacturing. The method identifies bridge risk regions and adjusts pattern positions in advance, so that when the semiconductor device is manufactured, the conductive patterns are pre-positioned to prevent bridging, thereby improving reliability without adding manufacturing complexity
Solution Approach 2:
The patent changes the spatial parameters of the layout by biasing (shifting) the line ends of conductive patterns away from bridge risk regions. This parameter adjustment ensures adequate spacing between adjacent conductive patterns, preventing electrical shorts while maintaining design flexibility
2Reliability
If conductive patterns are spaced out to prevent bridges, then reliability is improved, but area increases
Solution Approach 1:
The patent applies local quality by performing line-end biasing only in specific locations where bridge risk regions are identified, rather than uniformly spacing out all conductive patterns. This localized approach prevents bridges in critical areas while maintaining optimal spacing elsewhere, thus improving reliability without significant area penalty
Solution Approach 2:
The patent makes targeted parameter changes by adjusting only the positions of line ends adjacent to bridge risk regions, rather than increasing spacing across the entire layout. This selective parameter adjustment minimizes the area increase while effectively preventing electrical shorts
Data Source
AI summary
Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises providing a layout comprising a first group that includes first and second patterns and a second group that includes third and fourth patterns, examining a bridge risk region in the layout, biasing one end of at least one of the first and third patterns, and forming first to fourth conductive patterns by respectively using the first to fourth patterns of the layout. The one end of at least one of the first and third patterns are adjacent to the bridge risk region.