Semiconductor Line Pattern Fabrication via Surface-Modified Etch Masks
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Solution Overview
Problem
Current fine patterning technologies, such as double and quadruple patterning technologies, face challenges in forming precise and separated fine-width line patterns in semiconductor devices, leading to misalignment and reliability issues in electronic products.
Innovation Solution
A method involving the formation of reference patterns, spacers, and filling patterns on a substrate, followed by surface treatments to create surface-modified patterns, which are used as etch masks to selectively remove unwanted layers, allowing for the formation of line patterns with varying widths without removing the surface-modified features, thereby improving pattern separation and reducing the need for additional photolithography processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional fine patterning technologies (double patterning, quadruple patterning) are used to form fine line patterns, then line pattern density increases, but line separation precision deteriorates making it difficult to form fine-width line separation patterns
Solution Approach 1:
The patent segments the patterning process into multiple distinct stages: forming reference patterns, forming spacers on reference patterns, forming filling patterns between spacers, and performing selective surface treatments. This segmentation allows each stage to contribute specifically to the final line separation precision, with the surface-modified patterns serving as dedicated etch masks for creating fine-width line separations between densely packed line patterns
Solution Approach 2:
The patent introduces surface-modified reference patterns and filling patterns as intermediary etch masks that mediate between the densely packed line patterns and the final etched structure. These surface-modified patterns are selectively treated to have different etch resistance, allowing them to serve as precise guides for forming line separations without being removed in the etching process, thus enabling fine-width line separation even at high line pattern density
2Manufacturing precision
If additional photolithography processes are used to improve pattern separation precision, then line separation precision improves, but device complexity and fabrication cost increase
Solution Approach 1:
The patent makes the reference patterns and filling patterns multi-functional: they serve both as structural templates for defining line pattern positions and as etch masks for creating line separations. The surface treatment modifies these patterns to have different etch resistance properties, allowing them to perform dual functions without requiring additional photolithography steps, thus improving pattern separation precision while avoiding increased fabrication complexity
Solution Approach 2:
The patent changes the surface properties (etch resistance parameter) of reference patterns and filling patterns through selective surface treatment. This parameter change allows the same physical patterns to serve different functions during etching: surface-modified regions remain as etch masks while non-modified regions are removed, enabling precise line separation without adding process complexity
Data Source
AI summary
A method of fabricating a semiconductor device includes forming a target layer on a substrate, forming a plurality of reference patterns at uniform intervals on the target layer, forming a plurality of spacers on the side surfaces of the reference patterns, forming a plurality of filling patterns in spaces left between the spacers, forming a surface-modified filling pattern by performing a first surface treatment on a portion of the plurality of filling patterns, forming a surface-modified reference pattern by performing a second surface treatment on a portion of the plurality of reference patterns, and removing the plurality of filling patterns and the plurality of reference patterns and leaving the surface-modified filling pattern and the surface-modified reference pattern on the target layer.