Semiconductor Line Patterns Selective Etching via Mask Segmentation
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Solution Overview
Problem
The challenge in semiconductor device manufacturing is the difficulty in selectively etching fine patterns due to their narrow intervals, which leads to the unintended etching of peripheral patterns, making it hard to disconnect or connect specific patterns using existing double patterning methods.
Innovation Solution
The solution involves forming first and second line patterns in parallel on a semiconductor substrate, with connection structures coupling adjacent third and fourth line patterns, and using a method that includes forming via plugs, interlayer dielectric layers, etch mask patterns, and trenches to selectively etch and connect/disconnect patterns, allowing for the formation of fine patterns at narrower distances than the exposure equipment's limit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If double patterning method is used to form patterns at half the minimum distance of exposure equipment, then the interval between patterns is reduced, but it becomes difficult to selectively etch only one pattern because peripheral patterns may also be etched
Solution Approach 1:
The patent divides the etching process into multiple selective steps. First, a first etch mask pattern is formed to protect certain patterns while etching others. Then, a second etch mask pattern is formed to protect different patterns for the next etching step. This segmentation of the etching process into discrete, controlled steps enables selective disconnection of specific patterns even when patterns are formed at half the minimum exposure distance
Solution Approach 2:
The patent applies preliminary protective actions by forming etch mask patterns before each etching step. The first etch mask pattern is formed to protect patterns that should not be etched in the first etching step. The second etch mask pattern is formed beforehand to protect patterns that should remain intact for subsequent steps. These preliminary protective measures prevent unintended etching of peripheral patterns
2Productivity
If patterns are formed using double patterning method with narrow intervals, then the degree of integration is increased, but the complexity of selectively disconnecting or connecting specific patterns increases
Solution Approach 1:
The patent segments the pattern modification process into distinct phases: first etching to disconnect certain patterns, then forming connection structures to reconnect specific disconnected patterns, and finally performing additional etching if needed. This segmented approach to pattern disconnection and connection provides systematic control over complex pattern modifications while maintaining high integration
Solution Approach 2:
The patent introduces connection structures as intermediary elements between disconnected patterns. These connection structures serve as mediators that can selectively reconnect specific patterns after etching has disconnected them. The connection structures provide a controlled mechanism for managing pattern connectivity in highly integrated devices without requiring direct manipulation of the closely-spaced patterns
Data Source
AI summary
A semiconductor device includes a first line pattern and a second line pattern formed in parallel on a semiconductor substrate, third line patterns formed in parallel between the first line pattern and the second line pattern, fourth line patterns formed in parallel between the first line pattern and the second line pattern, a first connection structure configured to couple a first of the third line patterns with a first of the fourth lines patterns, which are adjacent to the first line pattern, and a second connection structure configured to couple a second of the first lines patterns with a second of the fourth lines patterns, which are adjacent to the second line pattern.