Semiconductor Line Patterns with Mirror Symmetry End-Portions
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Solution Overview
Problem
The challenge in semiconductor memory device fabrication is to achieve higher integration while preventing bridging between word lines, which is hindered by the limitations of current patterning technologies and the difficulty in maintaining pattern density during etching processes, leading to potential malfunctions.
Innovation Solution
The method involves forming semiconductor devices with line patterns and remaining line patterns having mirror symmetry end-portions, using a spacer trim process to prevent bridging by applying uniform etching conditions, and configuring dummy and cell active regions to confine any bridging within the dummy active region, thereby enhancing the line width and operational characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If current patterning technologies are used to achieve higher integration, then device density increases, but bridging between word lines occurs causing malfunctions
Solution Approach 1:
The patent applies preliminary action by forming a trim pattern on the end portions of word lines before the main etching process. This trim pattern serves as a pre-prepared structure that prevents bridging during subsequent etching operations. The trim pattern is formed at a stage prior to the critical etching step, allowing the etching process to proceed uniformly without causing bridging between closely spaced word lines, thus enabling higher integration while maintaining reliability.
Solution Approach 2:
The patent implements local quality by applying different processing treatments to different regions of the word lines. Specifically, the end portions of word lines receive a trim pattern formation treatment, while the main body portions undergo standard etching. This localized differentiation ensures that the critical end portions are protected from bridging while maintaining the overall device functionality and high integration density.
2Reliability
If pattern density is reduced during etching to prevent bridging, then reliability improves, but manufacturing precision deteriorates
Solution Approach 1:
The trim pattern is formed in advance on the end portions of word lines before the main etching process. This preliminary structure ensures that during the etching process, the end portions maintain proper spacing and prevent bridging without requiring reduction of overall pattern density. The pre-formed trim pattern acts as a spacer that maintains manufacturing precision while ensuring reliable pattern formation.
Solution Approach 2:
The patent applies local quality by treating only the end portions of word lines with the trim pattern formation process. This localized treatment maintains the line width and pattern density of the main body portions at their designed values, preserving manufacturing precision, while the trimmed end portions provide the necessary spacing to prevent bridging, thus improving reliability without sacrificing overall precision.
3Reliability
If line width is increased to prevent bridging, then reliability improves, but device integration density decreases
Solution Approach 1:
The trim pattern is formed in advance on the end portions of word lines, creating a protective structure that prevents bridging. This allows the main body of the word lines to maintain their designed narrow width, preserving high integration density, while the trimmed end portions provide the necessary spacing to prevent bridging, thus improving reliability without reducing overall integration.
Solution Approach 2:
The patent implements local quality by applying the trim pattern only to the end portions of word lines. This localized approach maintains the narrow line width and high integration density in the main device area, while the trimmed end portions locally increase the effective spacing to prevent bridging. This resolves the contradiction by improving reliability at critical locations without sacrificing overall integration density.
Data Source
AI summary
A semiconductor device includes a plurality of lines disposed on a semiconductor substrate, and remaining line patterns disposed spaced apart from the lines on extensions from the lines. The lines include first end-portions adjacent to the remaining line patterns. The remaining line patterns include second end-portions adjacent to the lines. The first end-portions and second end-portions are formed to have mirror symmetry with respect to each other.