Semiconductor Line Patterns Using Segmentation and Dimensionality Change
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Solution Overview
Problem
Current semiconductor technologies face challenges in downsizing line patterns below the resolution limit of photolithography processes, necessary for highly integrated semiconductor devices, which restricts the miniaturization and density of integrated circuit designs.
Innovation Solution
The semiconductor device incorporates line patterns with varying widths, including sub-line patterns and wide-width patterns, arranged with specific spacings to exceed the minimum feature size but remain below double the minimum feature size, allowing for conductive line patterns to be formed within trenches, enhancing design flexibility and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If line patterns are downsized to increase integration density, then integration density improves, but manufacturing precision deteriorates due to photolithography resolution limits
Solution Approach 1:
The patent divides a single wide line pattern into multiple narrower sub-line patterns (e.g., two or more lines) that are spaced apart. Each sub-line pattern has a width that can be manufactured within photolithography resolution limits, while the combined structure functions as a wider conductive line, thereby achieving both manufacturability and high integration density
Solution Approach 2:
The patent transitions from forming line patterns in a single dimension (width only) to using multiple dimensions by arranging sub-line patterns in both width and spacing dimensions. This allows the effective conductive width to be achieved through spatial arrangement rather than single-line width, overcoming photolithography resolution constraints
2Adaptability or versatility
If line pattern width is reduced below photolithography resolution limit, then design flexibility improves, but manufacturing precision deteriorates
Solution Approach 1:
The patent segments wide line patterns into multiple narrower sub-line patterns, where each segment's width remains within photolithography manufacturing capabilities. This segmentation allows designers to achieve effective wide-line functionality while maintaining manufacturable individual pattern dimensions
Solution Approach 2:
The patent introduces spacer structures as intermediary elements between sub-line patterns. These spacers serve as mediators that define the spacing between conductive sub-lines while allowing the overall structure to function as a wider effective conductor, bridging the gap between manufacturable narrow lines and desired wide-line functionality
Data Source
AI summary
Provided is a semiconductor device. The device includes a plurality of line patterns, which extend in a first direction and are arranged a first space apart from one another in a second direction perpendicular to the first direction. The line patterns include a line pattern set including two sub-line patterns that are arranged the first space apart from each other in the second direction and have a first width of a minimum feature size (1F) in the second direction, and a wide-width line pattern that is arranged the first space apart from one side of the line pattern set in the second direction and has a second width larger than the first width in the second direction.