Semiconductor Load Board Testing System for Stacked Devices
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Solution Overview
Problem
The semiconductor industry faces challenges in efficiently testing and identifying defects in large, complex semiconductor devices, particularly in stacked and bonded structures, where traditional testing methods are inefficient and often performed on individual components rather than the entire device.
Innovation Solution
A system-on-wafer (SoW) testing system is developed, which includes connector structures and test structures that interface with the device's connectors and sockets, allowing for system-scale electrical testing. This system enables testing of the entire device after processing, facilitating connector continuity tests and improving testing efficiency by forming continuous conductive paths through the device's redistribution structure, sockets, and test structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional testing methods are used on individual components, then testing process is simple, but testing efficiency is low and defect identification is incomplete
Solution Approach 1:
The patent merges multiple individual component testing operations into a single system-level testing operation. The load board integrates multiple device under test (DUT) positions with shared electrical connections, allowing simultaneous testing of multiple semiconductor devices. This combining approach increases productivity by testing entire assemblies rather than individual components separately, while the standardized load board design keeps the complexity manageable through reuse of testing resources.
Solution Approach 2:
The load board serves multiple functions: it provides electrical connections for power and signal distribution, mechanical support for multiple DUTs, thermal management pathways, and defect localization capabilities. This multi-functionality allows a single testing system to handle various testing requirements (functional testing, defect identification, yield analysis) without requiring separate specialized equipment for each function, thereby improving productivity while controlling complexity.
2Measurement precision
If system-scale electrical testing is implemented, then defect identification improves, but testing system complexity increases
Solution Approach 1:
The testing system segments the semiconductor device into multiple device under test (DUT) positions on the load board, each with dedicated electrical connections for independent defect identification. This segmentation allows the system to pinpoint defects to specific devices or regions within the semiconductor assembly, improving measurement precision for defect localization while maintaining manageable complexity through modular connection design.
Solution Approach 2:
The load board acts as an intermediary between the testing equipment and the semiconductor devices. It provides standardized electrical interfaces that simplify the connection complexity, while enabling sophisticated system-level testing and defect identification. The load board's standardized connection architecture mediates between the simple act of connecting devices and the complex task of system-level electrical testing and analysis.
3Reliability
If individual component testing is performed, then testing setup is simple, but yield analysis is insufficient
Solution Approach 1:
The patent combines multiple device testing operations into a single integrated testing process on the load board. By testing multiple semiconductor devices simultaneously in their assembled configuration, the system enables comprehensive yield analysis that captures interactions between components and identifies defects that would be missed in isolated component testing. This merging approach improves reliability of yield data while the standardized load board design keeps the process complexity manageable through reuse of testing resources.
Data Source
AI summary
A testing system includes a load board that includes a first circuit board, a first external connector attached to the first circuit board, and a thermal module configured to hold a system-on-wafer structure including a connector and a socket, a connector structure including a second circuit board, wherein the second circuit board is electrically connected to the first external connector, and a second external connector configured to connect to the connector of the system-on-wafer structure, and a test structure configured to connect to the socket of the system-on-wafer structure, the test structure including a third circuit board and pins, wherein adjacent pairs of pins of the test structure are electrically coupled through the third circuit board to form a continuous conductive path extending alternately between the system-on-wafer structure and the adjacent pairs of pins of the test structure.