Semiconductor Integrated Circuit Local Buried Layers Noise Tolerance
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Solution Overview
Problem
High voltage integrated circuits (HVICs) face challenges in noise tolerance due to the activation of parasitic pnp bipolar transistors, which can lead to malfunction and damage from voltage surges, and existing solutions that increase noise tolerance either decrease the DC current amplification factor or increase chip area.
Innovation Solution
A semiconductor integrated circuit design with locally buried n+-type buried layers under specific well regions and electrode regions, avoiding even burial across the high side circuit region to minimize parasitic capacitance and maintain noise tolerance without increasing chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an n-type buried layer having a high concentration is buried evenly along the interface between the n-well region and the p-type substrate in the high side circuit region, then the DC current amplification factor of the parasitic pnp bipolar transistor is decreased and noise tolerance is improved, but the junction capacitance increases leading to increased displacement current and potential malfunction
Solution Approach 1:
The patent applies local quality by selectively positioning n-type buried layers only under the p-well region and main electrode region where parasitic transistor activation is most critical, rather than uniformly distributing them across the entire high side circuit region. This localized approach reduces overall junction capacitance while maintaining noise tolerance at critical interfaces.
Solution Approach 2:
The patent segments the buried layer structure into multiple discrete n-type buried layers positioned at specific locations (under p-well region and main electrode region) rather than using a single continuous buried layer. This segmentation reduces total capacitance while providing targeted protection against parasitic transistor activation.
2Reliability
If the distance between the low side circuit region and the high side circuit region is increased to prevent displacement current flow, then noise tolerance is improved, but the chip area increases
Solution Approach 1:
The patent applies local quality by concentrating noise protection measures (n-type buried layers) at specific critical interfaces within the high side circuit region rather than increasing overall circuit separation. This allows maintaining compact chip area while providing targeted protection where parasitic transistor activation is most likely.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively prevents parasitic pnp bipolar transistor activation from noise, maintaining high noise tolerance and reducing displacement current effects while minimizing chip area expansion.
Implementation Method 1
a capacitance at the junction between the n-type buried layer and the p-type substrate increases when the n-type buried layer having a high concentration is buried in the high side circuit region evenly along the interface between the n-well region and the p-type substrate
Data Source
AI summary
A semiconductor integrated circuit includes: a semiconductor base body of a first conductivity type; a first well region of a second conductivity type, deposited at an upper portion of the semiconductor base body, to which a first potential is applied; a second well region of the first conductivity type, deposited at an upper portion of the first well region, to which a second potential lower than the first potential is applied; a main electrode region to which the second potential is applied, the main electrode region being deposited at the upper portion of the first well region and away from the second well region; a first buried layer of the second conductivity type buried locally under the second well region; and a second buried layer of the second conductivity type buried locally under the main electrode region and away from the first buried layer.