High-Voltage Semiconductor Device Local Doping for Punch-Through Prevention
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Solution Overview
Problem
Traditional high-voltage semiconductor devices face challenges with increased on-resistance due to larger channel lengths, which also result in higher on-resistance for P-type devices compared to N-type devices, making them less favorable.
Innovation Solution
A high-voltage semiconductor device structure is developed with an epitaxial layer, gate structure, and stack structure that includes a blocking layer, insulating layer, and conductive layer to decrease electric field density and on-resistance, utilizing different conductive types for well regions and doping regions to improve device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel length is increased to prevent punch-through between source and drain, then the device reliability is improved, but the on-resistance and chip area increase
Solution Approach 1:
The patent applies local quality by creating a high-voltage well region with different doping concentration specifically in the channel area between source and drain. This localized doping modification increases the potential barrier in the channel, preventing punch-through without requiring an overall increase in channel length, thus maintaining low on-resistance while ensuring device reliability.
2Reliability
If the channel length is increased to prevent punch-through, then the device reliability is improved, but the chip area increases
Solution Approach 1:
The patent modifies only the doping concentration in the channel region locally, rather than increasing the physical dimensions of the device. This localized doping approach prevents punch-through by creating an electrical barrier without expanding the chip area, thus resolving the contradiction between reliability and area.
3Adaptability or versatility
If P-type high-voltage semiconductor devices are used, then the device structure is formed, but the on-resistance is higher compared to N-type devices due to lower hole mobility
Solution Approach 1:
The patent changes the doping concentration parameter in the high-voltage well region to compensate for the lower hole mobility in P-type devices. By optimizing the doping concentration, the patent improves the electrical characteristics and reduces on-resistance of P-type high-voltage semiconductor devices, making them more competitive with N-type devices.
Data Source
AI summary
A high-voltage semiconductor device is provided. The high-voltage semiconductor device includes a substrate; an epitaxial layer and a gate structure; a first conductive type first high-voltage well region and a second conductive type high-voltage well region disposed in the epitaxial layer at opposite sides of the gate structure respectively, wherein the first conductive type is different from the second conductive type; a source region and a drain region; and a stack structure disposed between the gate structure and the drain region, wherein the stack structure includes: a blocking layer; an insulating layer disposed over the blocking layer; and a conductive layer disposed over the insulating layer and electrically connected the source region or the gate structure. A method for manufacturing the high-voltage semiconductor device is also provided.