Semiconductor Local Interconnect Structure Staggered Trench Etching
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Solution Overview
Problem
The manufacturing process of local interconnect structures in FinFET devices below 20 nm technology nodes requires high accuracy and complexity due to small feature sizes and high density, particularly with the need for double patterning lithography, which poses challenges in patterned mask and etching coverage.
Innovation Solution
A method involving a semiconductor substrate with gates and dielectric layers, where a first interconnect trench is formed, followed by a metal silicide layer and a first metal layer, then a second dielectric layer with a staggered second interconnect trench, and finally a third interconnect trench, all filled with metal layers to form a local interconnect structure, reducing the need for double patterning and improving step coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If double patterning lithography is used to form small-size local interconnect structures, then manufacturing precision is improved, but device complexity and process difficulty increase
Solution Approach 1:
The patent divides the formation of interconnect structures into separate stages: first forming trenches in the first dielectric layer, then forming trenches in the second dielectric layer. This segmentation allows each etching process to be optimized independently, achieving high precision without requiring complex double patterning lithography for the entire structure.
Solution Approach 2:
The patent transitions from a planar interconnect approach to a three-dimensional stacked architecture with first and second dielectric layers at different vertical levels. This dimensional change enables the formation of complex interconnect patterns through sequential etching processes, avoiding the need for double patterning lithography while maintaining high precision.
2Manufacturing precision
If double patterning lithography is used, then manufacturing precision is improved, but ease of manufacture deteriorates
Solution Approach 1:
The manufacturing process is segmented into distinct etching stages for the first and second dielectric layers. Each stage uses a separate mask and etching process, allowing standard lithography tools to be used without requiring complex double patterning equipment, thereby improving ease of manufacture while maintaining pattern accuracy.
Solution Approach 2:
The first interconnect trenches are formed and filled with metal layers before forming the second dielectric layer and its trenches. This preliminary action establishes a stable foundation that simplifies subsequent processing steps and improves overall manufacturability.
3Adaptability or versatility
If separate trench formation is used for first and second interconnect layers, then manufacturing flexibility is improved, but manufacturing precision deteriorates due to high accuracy requirements on masks and etching coverage
Solution Approach 1:
The first interconnect trenches serve as self-aligned references for the second etching process. The staggered arrangement of trenches in the second dielectric layer relative to the first layer creates overlapping regions that automatically define precise alignment boundaries, reducing the accuracy requirements for external masks and etching processes.
Solution Approach 2:
By separating the trench formation into distinct stages for different dielectric layers with staggered patterns, the patent achieves both manufacturing flexibility and precision. Each etching process targets specific regions independently, allowing flexible design while maintaining high precision through the staggered geometry rather than relying on high-accuracy single-step patterning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process by eliminating the need for double patterning lithography, reducing design constraints, and enhancing the performance of the local interconnect structure with improved metal silicide layer step coverage.
Implementation Method 1
performing a first etching process on the first dielectric layer to form a first interconnect trench
Implementation Method 2
forming a metal silicide layer at a bottom of the first interconnect trench
Data Source
AI summary
A method for manufacturing a semiconductor device having a local interconnect structure includes providing a semiconductor substrate having a gate on an active region, a hardmask layer on the gate, and a first dielectric layer on the gate, etching the first dielectric layer to form a first interconnect trench on the active region, forming a metal silicide layer at a bottom of the first interconnect trench, forming a first metal layer filling the first interconnect trench, forming a second dielectric layer on the gate and the first interconnect trench, etching the second dielectric layer to form a second interconnect trench in a staggered pattern relative to the first interconnect trench, etching the second dielectric layer to form a third interconnect trench, forming a second metal layer in the second interconnect trench and in the third interconnect trench to form the local interconnect structure.