Semiconductor Local Interconnects for Logic Area Reduction
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Solution Overview
Problem
As semiconductor devices shrink, traditional cross-coupling methods using standard metal layers become inefficient, leading to increased area occupation and reduced functionality, especially at the 20 nm node, where lithographic limitations hinder the scaling of standard cell library devices.
Innovation Solution
The implementation of CA and CB local interconnect layers, electrically connected to transistors' sources, drains, and gates, which bypass the need for standard metal layers, allowing for cross-coupling and reducing the area occupied by logic elements in semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional cross-coupling utilizing standard metal layer is used, then transistors can be cross-coupled to enable logic scaling, but large amounts of area are occupied
Solution Approach 1:
The patent transitions from planar metal layer interconnects to three-dimensional local interconnects formed within trenches. The CA and CB interconnect layers are positioned at different vertical levels and connected through vias, creating a vertical stacking architecture that reduces lateral area occupation while maintaining cross-coupling functionality between transistors
Solution Approach 2:
The interconnect structure is divided into separate functional segments: CA (contact access) layers for source/drain connections, CB (buried contact) layers for gate connections, and intermediate interconnect layers. This segmentation allows independent optimization of each layer's function and enables compact arrangement that reduces overall area
2Length of moving object
If standard cell library devices are scaled down, then device size decreases, but lithographic limitations at 20 nm node prevent further scaling
Solution Approach 1:
The patent moves critical interconnect functions from the lateral plane to the vertical dimension by forming CA and CB layers at different depths within the semiconductor structure. This vertical stacking enables continued scaling at 20 nm node by bypassing lithographic resolution limits that constrain planar feature sizes
3Area of stationary object
If cross-coupling is implemented without standard metal layer, then area is conserved, but alternative interconnect structure must be created
Solution Approach 1:
The patent merges the functions of contact access, interconnection, and insulation into integrated CA and CB layer structures. These layers serve multiple purposes: providing electrical connections, acting as interconnect pathways, and being surrounded by insulating materials that provide electrical isolation, thereby reducing the need for separate structural elements
Data Source
AI summary
A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors includes a source, a drain, and a gate. A CA layer is electrically connected to at least one of the source or the drain of the first transistor. A CB layer is electrically connected to at least one of the gates of the transistors and the CA layer.