Semiconductor Device with Local Quality Gate Dielectric
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional voltage level shift circuits require larger chip areas due to the similar size and structure of medium and high voltage devices, leading to increased costs and reduced performance due to low saturated current in medium voltage devices.
Innovation Solution
A semiconductor device is fabricated with a high voltage device, a medium voltage device, and a low voltage device on a single chip, where the medium voltage device has a thinner gate dielectric layer and higher saturated current, reducing overall dimensions and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the medium voltage device uses the same gate dielectric layer thickness as the high voltage device, then the device structure is simplified and manufacturing is easier, but the saturated current becomes small and performance deteriorates
Solution Approach 1:
The patent applies local quality by forming a first gate dielectric layer with different thicknesses in different regions: a first thickness in the high voltage device region and a second thickness (greater than the first) in the medium voltage device region. This allows each device type to have optimized gate dielectric thickness for its specific voltage requirements, improving saturated current in the medium voltage device while maintaining the high voltage device's breakdown characteristics.
2Device complexity
If the medium voltage device uses the same size and structure as the high voltage device, then the device design is simplified, but the occupied chip area increases and cost rises
Solution Approach 1:
The patent implements local quality through differentiated gate dielectric layer thicknesses for different device regions, allowing the medium voltage device to achieve higher saturated current with smaller dimensions compared to using the same structure as the high voltage device. This reduces the overall chip area occupied by voltage level shift circuitry.
3Area of stationary object
If multiple voltage level devices are integrated on a single chip, then the chip size is reduced and cost decreases, but the fabrication process complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the gate dielectric formation into sequential steps: first forming a first gate dielectric layer across the entire substrate, then selectively removing portions in the medium voltage region, and finally forming a second gate dielectric layer with greater thickness in the medium voltage region. This segmented approach enables multi-voltage device integration on a single chip with optimized performance for each device type.
Data Source
AI summary
A method of fabricating a semiconductor device utilizes a substrate including a high voltage circuit area, a medium voltage circuit area and a low voltage circuit area. A first well of a first conductivity type is formed. Two separate second wells of a second conductivity type are formed in the first well and two separate isolation structures are formed respectively in the second wells in each of the high voltage circuit area and the medium voltage circuit area. A first gate dielectric layer is formed in the high voltage circuit area. A second gate dielectric layer that is thinner than the first gate dielectric layer is formed in each of the medium voltage circuit area and the low voltage circuit area. A gate is formed. Two source and drain regions of the second conductivity type are respectively formed. The method is simple and low-cost and meets the market requirement.