Semiconductor Device With Local Quality Gate Dielectrics
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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multi-functional electronic devices necessitates improved integration density and reliability in semiconductor devices, particularly in transistor scaling, which existing technologies have not adequately addressed.
Innovation Solution
A semiconductor device design incorporating a memory cell region with memory cells arranged along channel holes and a peripheral circuit region featuring low voltage transistors with a high-k material gate dielectric layer and metal gate electrode, and high voltage transistors with a silicon dioxide gate dielectric layer and polysilicon gate electrode, optimized for different operational voltages and functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single gate dielectric layer is used for all transistors, then manufacturing process is simplified, but performance optimization for different voltage requirements cannot be achieved
Solution Approach 1:
The patent applies local quality by using different gate dielectric layers in different regions: a first gate dielectric layer for low voltage transistors and a second gate dielectric layer for high voltage transistors. This allows each transistor type to have optimized electrical characteristics suited to its specific voltage requirements, resolving the contradiction between manufacturing simplicity and performance optimization.
Solution Approach 2:
The patent segments the gate dielectric structure into multiple distinct layers: a first gate dielectric layer formed in a first region for low voltage transistors, and a second gate dielectric layer formed in a second region for high voltage transistors. This segmentation enables independent optimization of dielectric properties for different voltage applications while maintaining a systematic manufacturing approach.
2Productivity
If transistor scaling is increased to improve integration density, then more functions can be integrated, but reliability and performance become difficult to maintain
Solution Approach 1:
The patent applies local quality by providing different gate dielectric layer configurations for different transistor types within the integrated circuit. Low voltage transistors receive a first gate dielectric layer optimized for high-speed operation, while high voltage transistors receive a second gate dielectric layer optimized for voltage handling. This allows the circuit to achieve high integration density while maintaining reliable performance across different operational requirements.
Data Source
AI summary
A semiconductor device includes a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate, and a peripheral circuit region disposed outside of the memory cell region and including low voltage transistors and high voltage transistors. The low voltage transistors include first transistors including a first gate dielectric layer and a first gate electrode layer including a metal, and the high voltage transistors include second transistors including a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon.