Semiconductor Logic Device Embedded Packaging Redistribution Layer
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Solution Overview
Problem
High-end semiconductor logic devices face challenges in miniaturization due to limitations in flip chip solder bump technology, including high resistance losses, electro-migration susceptibility, and low yields in embedded chip packaging, especially for complex devices with high I/O pad counts.
Innovation Solution
A reconfigured semiconductor logic device with a redistribution layer featuring larger discrete terminal pads electrically coupled to I/O pads through conductive vias, allowing for reduced pad pitch and improved interconnect yields, and an electronics package with a multi-layer interconnect structure forming parallel electrical connections without solder.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flip chip solder bump technology is used for high I/O pad count devices, then electrical connection is achieved, but resistance losses increase and electro-migration susceptibility worsens
Solution Approach 1:
The patent extracts the solder bump interconnect function and replaces it with a direct wire bond connection to a reduced number of I/O pads. By removing the solder bump layer and its associated resistance, the design achieves lower resistance losses while maintaining electrical connection functionality through alternative bonding methods.
Solution Approach 2:
The patent introduces wire bonds as an intermediary connection method between the semiconductor device and the substrate. This intermediary approach replaces the direct solder bump connection, providing a more reliable electrical path that is less susceptible to electro-migration and resistance losses.
2Power
If I/O pad count is increased to meet power and ground current requirements, then current delivery capability is improved, but chip size increases
Solution Approach 1:
The patent merges multiple power and ground I/O pad functions into a reduced number of larger I/O pads. By consolidating the current delivery function into fewer pads with higher individual current capacity, the design maintains power delivery capability while reducing the total number of pads required and thus reducing chip size.
Solution Approach 2:
The patent changes the parameters of the I/O pads by reducing their quantity while increasing their individual size and current handling capability. This parameter transformation allows the same total power delivery capability to be achieved with fewer pads, thereby reducing the chip area required for I/O structures.
3Productivity
If minimum solderable pitch is used for I/O pad array, then assembly yield is maintained, but die size cannot be reduced further
Solution Approach 1:
The patent extracts the solder bump attachment requirement entirely from the design. By removing the constraint of minimum solderable pitch, the design can use smaller pad pitches that would otherwise be unsuitable for solder bump assembly, thereby enabling further die size reduction while maintaining assembly yield through wire bond technology.
4Productivity
If feature size is reduced to increase gates per unit area, then functionality per chip is improved, but minimum pad pitch constraint prevents further size reduction
Solution Approach 1:
The patent replaces the durable but constraint-imposing solder bump interconnect structure with a different interconnection approach that allows for smaller feature sizes. By using wire bonds instead of solder bumps, the design can exploit smaller minimum feature sizes achieved through advanced fabrication nodes without being limited by solderable pitch constraints, thereby increasing gates per unit area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables die size reduction while maintaining power and ground signal delivery, increasing chip density, and reducing fabrication costs by enhancing interconnect performance and yield, and eliminating solder-related issues like fatigue and shorting.
Implementation Method 1
The plurality of discrete terminal pads are electrically coupled to respective I/O pads of the plurality of I/O pads by conductive vias formed through the insulating layer
Implementation Method 2
Solder bumps 22 are attached to each I/O pad 12, 14, 16 and reflowed to attach the device 10 to the upper pads 24 of the multi-layer interconnect structure 18
Implementation Method 3
Interconnect structure 18 has multiple interconnect layers 26, each comprising an insulating layer 28, a wiring layer 30, and metallized vias 32 formed through the insulating layer 28
Data Source
AI summary
A reconfigured semiconductor logic device includes a semiconductor logic device comprising an active surface having a plurality of input/output (I/O) pads formed thereon and a redistribution layer. The redistribution layer includes an insulating layer disposed on the active surface of the semiconductor logic device and a patterned conductive layer comprising a plurality of discrete terminal pads formed atop the insulating layer. The plurality of discrete terminal pads are electrically coupled to respective I/O pads of the plurality of I/O pads by conductive vias formed through the insulating layer. The plurality of discrete terminal pads are larger than the plurality of I/O pads.