Semiconductor Device Logic Level Conversion for Interference Reduction
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Solution Overview
Problem
As semiconductor processes become finer, the increasing interference between data bits due to smaller memory cell sizes and narrower signal transmission lines leads to inter-symbol and inter-channel interference phenomena, which existing technologies have not adequately addressed.
Innovation Solution
A semiconductor system comprising a first semiconductor device for outputting commands and addresses, and a second semiconductor device with a pattern control block that converts logic level combinations of data only when a flag signal indicates a different logic level among the bits, thereby reducing interference by adjusting data levels during write and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor processes are scaled down to increase integration and operation speed, then memory capacity and operation speed are improved, but interference between data bits increases causing inter-symbol and inter-channel interference
Solution Approach 1:
The patent changes the parameter of data representation by converting between different logic level combinations (e.g., from normal polarity to inverted polarity). This parameter transformation allows the system to maintain high-speed operation while reducing interference effects, as the converted data patterns exhibit lower susceptibility to inter-symbol and inter-channel interference
Solution Approach 2:
The patent applies preliminary conversion action to data before it is written to or read from memory. By pre-converting the logic level combinations based on detected patterns, the system proactively eliminates interference issues before they occur during normal memory operations, thereby maintaining high productivity without interference penalties
2Quantity of substance
If memory cell size and line width are reduced to increase integration, then device density is improved, but interference phenomenon between data bits increases
Solution Approach 1:
The patent transforms the parameter of data logic levels to create patterns that are less susceptible to interference. By converting between different logic level combinations based on detected data patterns, the system achieves high integration density while mitigating the interference effects that naturally arise from smaller cell sizes and narrower transmission lines
3Ease of operation
If data is written and read without logic level conversion, then operation simplicity is maintained, but interference between data bits increases
Solution Approach 1:
The patent implements a self-service mechanism where the memory system automatically detects data patterns and performs logic level conversion when interference is anticipated. The pattern detection circuit and conversion circuit work autonomously within the memory device, requiring no external intervention while effectively reducing interference between data bits during normal operations
Data Source
AI summary
A semiconductor system may include a first semiconductor device configured to output commands, addresses and data. The semiconductor system may include a second semiconductor device configured to convert a logic level combination of the data when only any one of bits of the data is a different logic level, and store the data in response to the commands and the addresses, in a write operation.