Semiconductor Logic and Memory Integration via Dual Polysilicon Layers
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Solution Overview
Problem
Existing semiconductor devices face challenges in integrating low voltage transistors, EEPROM cells, and flash memory cells on a single chip due to compatibility issues and size constraints, leading to increased processing time and inventory management difficulties.
Innovation Solution
A method for fabricating a semiconductor device involves forming a substrate with distinct regions for logic, EEPROM, and flash memory cells, using a stack structure with floating gates, inter-poly dielectric layers, and polysilicon layers to create control gates and gate electrodes, allowing for independent operation of EEPROM and flash memory cells while reducing chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If flash memory cell is used to embody mask ROM device, then coding flexibility is improved, but device operation complexity increases due to sector division requirements
Solution Approach 1:
The substrate is divided into three distinct regions: a first region for logic devices, a second region for EEPROM cells, and a third region for flash memory cells. This spatial segmentation allows each region to be optimized for its specific function, enabling the flash memory region to operate in EEPROM mode without affecting other device operations.
Solution Approach 2:
Different regions of the substrate are assigned different functional qualities: the second region is configured with tunnel oxide layers and floating gates suitable for EEPROM operation, while the third region uses stacked gate structures for flash memory. This local differentiation enables the flash memory cell to perform byte-unit removal operations when needed.
2Adaptability or versatility
If EEPROM cell is used to embody mask ROM device, then coding flexibility is improved, but chip size increases due to larger cell area
Solution Approach 1:
The semiconductor device integrates multiple memory types (EEPROM and flash memory) and logic devices on a single substrate, allowing the system to achieve high memory integration while maintaining the ability to perform byte-unit removal operations through the flash memory cell operating in EEPROM mode.
Solution Approach 2:
The patent embeds multiple functional regions within a unified substrate structure, with the second region (EEPROM) and third region (flash memory) coexisting alongside the first region (logic devices). This nested arrangement maximizes space utilization and reduces overall chip size.
3Reliability
If mask ROM device is coded once, then security is improved, but inventory management difficulty increases
Solution Approach 1:
The device incorporates flash memory cells that can be dynamically programmed and erased after wafer fabrication, unlike traditional mask ROM devices that are fixed once coded. This dynamic reconfigurability allows inventory to be updated and adapted to different clients' needs, significantly improving inventory management flexibility while maintaining security through controlled access.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables stable integration of logic, EEPROM, and flash memory cells on a single chip, reducing processing time and inventory burdens, while maintaining memory capabilities and allowing for independent removal operations.
Implementation Method 1
a tunnel oxide layer is formed on the substrate
Implementation Method 2
a polysilicon layer is formed on the tunnel oxide layer
Data Source
AI summary
A method for fabricating a semiconductor device for a system on chip (SOC) for embodying a transistor for a logic device, an electrical erasable programmable read only memory (EEPROM) cell and a flash memory cell in one chip is provided. Floating gates of the EEPROM cell and the flash memory cell are formed by using a first polysilicon layer; and a gate electrode of the logic device and control gates of the EEPROM cell and the flash memory cell are formed by using a second polysilicon layer. Thus, it is possible to stably form the logic device, the EEPROM cell and the flash memory cell in one chip.