Semiconductor Logic Verification via Divisional Memory Model
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Solution Overview
Problem
The existing methods for verifying logic equivalence in semiconductor integrated circuits, especially after sub-banking of memory, are inefficient due to the lengthy process of logic simulation and subsequent design operations, making it impractical to perform sub-banking after logic simulation.
Innovation Solution
A verification apparatus and method that uses a divisional memory model for formal verification, treating the memory as a black box and verifying logic equivalence before and after modification by replacing the memory with a model that matches in input and output pins, reducing the time required for logic verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If logic simulation is performed for logic verification after sub-banking of memory, then logic equivalence can be verified, but verification time becomes excessively long
Solution Approach 1:
The patent creates a copy of the memory circuit at the RTL level to serve as a reference model for formal verification. This copy is used to generate expected behavior patterns that are then compared against the gate-level netlist, eliminating the need for time-consuming logic simulation while maintaining verification reliability
Solution Approach 2:
The patent replaces the mechanical logic simulation process with a formal verification method that uses symbolic representation and mathematical proof. Instead of simulating each clock cycle, the system uses formal methods to mathematically prove equivalence between RTL and gate-level designs, dramatically reducing verification time
2Measurement precision
If gate level simulation is performed for large-scale integrated circuit, then detailed verification is achieved, but simulation time becomes impractically long
Solution Approach 1:
The patent extracts the essential verification function from the gate-level netlist by creating an RTL-level copy that captures only the critical behavioral characteristics. This extracted model is sufficient for equivalence verification and eliminates the computational burden of simulating every gate-level detail
Solution Approach 2:
The patent segments the verification process into two distinct phases: first, generating expected patterns from the RTL copy; second, comparing these patterns against gate-level simulation results. This segmentation allows the system to use the more efficient RTL model for the majority of verification work while still achieving detailed gate-level verification where necessary
Data Source
AI summary
The verification apparatus for a semiconductor integrated circuit verifies a logic equivalence before and after modification to the circuit by replacing a memory with a divisional memory model that agrees with the memory in number of input and output pins and verifying logics at an input and an output thereof.